Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-05-08
2007-05-08
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C257SE21577, C257SE21579
Reexamination Certificate
active
10313491
ABSTRACT:
Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.
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Jiang Ping
Kirmse Karen H. R.
Kraft Rob
Xing Guoqiang
Zielinski Eden
Brady III W. James
Garner Jacqueline J.
Ghyka Alexander
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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