Methods for forming patterned platinum layers using masking...

Details Methods for forming patterned platinum layers using masking... Methods for forming patterned platinum layers using masking...

1999-06-03

2001-02-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S669000, C438S742000, C216S051000, C216S072000, C216S075000

Reexamination Certificate

active

06187686

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of microelectronics and more particularly to the field of patterning microelectronic layers.
BACKGROUND OF THE INVENTION
As integrated circuit memory devices become more highly integrated, the demand for high performance gate electrodes increases. In particular, as memory capacities of dynamic random access memories (DRAM) exceed 1 gigabit, gate electrodes made from materials having a low resistivity and a work function corresponding to half the energy gap of silicon are needed. Currently, polycide structures including a silicide (a heat-treated compound of metal and silicon) which is formed on polysilicon are used to form gate electrodes. In particular, tungsten silicide and titanium silicide are widely used in these polycide structures.
As gate electrode materials improve, the resistance thereof decreases, and memory devices using these improved gate electrode materials can perform operations more quickly. Other problems may, however, result. For example, a titanium-polycide gate electrode can have a resistivity which is about one quarter that of a comparable tungsten-polycide gate electrode. When a titanium-polycide gate electrode is etched, however, the sidewalls of the gate electrode pattern may be eroded significantly. This erosion problem may be reduced by using low temperature test processes or time modulation systems. These approaches, however, may reduce process margins.
Platinum-polysilicon gate electrode structures are currently being studied to address the above mentioned problems. In particular, a platinum-polysilicon gate electrode structure can be used to reduce the gate electrode resistivity, to reduce erosion of gate electrode sidewalls, and to reduce the complexity of the gate electrode structure. For example, the resistances of various materials used to form comparable gate electrode structures are as follows: the resistance of a tungsten polycide gate can be approximately 80 &mgr;&OHgr;·cm; the resistance of a titanium polycide gate can be approximately 20 &mgr;&OHgr;·cm; and the resistance of a platinum polysilicon gate can be approximately 10 &mgr;&OHgr;·cm.
Platinum, however, is so chemically stable that it does not readily produce compounds having significantly high vapor pressures. Accordingly, platinum may be difficult to etch. When a platinum layer is etched using a photoresist mask and a chlorine series plasma gas, the photoresist may be etched more quickly than the platinum film. Accordingly, a photoresist mask may be insufficient when etching platinum making it difficult to form patterns having relatively high resolutions. The etching selectivity with respect to the photoresist is higher when a fluorine-series plasma gas is used to etch platinum. After etching a platinum layer using a fluorine-series gas, however, significant polymeric residues may be produced on the sidewalls of the patterned platinum layer.
Furthermore, when a fluorine-series plasma gas is used to etch a platinum layer, oxide may be etched too quickly to act as a mask. When a chlorine-series plasma gas is used, an oxide mask may be damaged. An oxide mask should thus be five times thicker than the platinum layer being patterned. Accordingly, an oxide mask may generate micro loading problems during the formation of patterns having relatively high resolutions. In addition, an adhesion layer may be needed to bond the platinum layer and the oxide layer which is used to form the oxide mask.
SUMMARY OF THE INVENTION
It is therefor an object of the present invention to provide improved methods for forming patterned platinum layers and related structures.
It is another object of the present invention to provide improved methods for forming gate electrodes and related structures.
It is still another object of the present invention to provide methods for forming patterned platinum layers having reduced sidewall erosion and residue generation, and related structures.
These and other objects are provided according to the present invention by methods including the steps of forming a platinum layer on a microelectronic substrate, forming a mask layer on the platinum layer wherein the mask layer comprises a mask material including titanium, and selectively removing exposed portions of the platinum layer to form the patterned platinum layer. A high degree of etching selectivity between the platinum layer and the mask layer can thus be achieved thereby reducing sidewall erosion and residue generation.
More particularly, mask materials including titanium and titanium nitride may provide a high degree of etch selectivity. The step of selectively removing exposed portions of the platinum layer can include etching the exposed portions of the platinum layer using a gas mixture including chlorine Cl
2
and oxygen O
2
. A mixture including at least 40% oxygen can further increase the selectivity of the etch.
The step of forming the platinum layer can be preceded by the step of forming a barrier layer on the microelectronic substrate. This barrier layer can protect the microelectronic substrate during the step of removing the exposed portions of the platinum layer. The barrier layer preferably comprises a material including titanium, such as titanium or titanium nitride. As discussed above, these materials have a high etching selectivity with respect to platinum so that the platinum layer can be etched without significantly damaging the barrier layer or the microelectronic substrate below the barrier layer. As will be understood by those having skill in the art, the microelectronic substrate can be defined to include a semiconductor substrate as well as oxide and polysilicon layers on the semiconductor substrate.
According to alternate aspects of the present invention, methods for forming a gate electrode structure on a microelectronic substrate are also provided. These methods include the steps of forming a polysilicon layer on the microelectronic substrate, forming a platinum layer on the polysilicon layer opposite the substrate, and forming a mask layer on the platinum layer. In particular, the mask layer defines exposed portions of the platinum layer, and the mask layer comprises a mask material including titanium. The exposed portions of the platinum layer are then selectively removed thereby defining exposed portions of the polysilicon layer. The exposed portions of the polysilicon layer are then removed completing the gate structure.
According to still other aspects of the present invention, microelectronic structures are provided. In particular, microelectronic structures according to the present invention can include a platinum layer on a microelectronic substrate, and a mask layer on the platinum layer wherein the mask layer comprises a mask material including titanium. In particular, the platinum layer and the mask layer can together define a mesa structure on the microelectronic substrate, and the mask material can be chosen from the group consisting of titanium and titanium nitride.
According to the methods and structures of the present invention, a titanium or titanium nitride mask can be used when patterning a platinum layer to reduce sidewall erosion thereof. In addition, the generation of residues can be reduced. The reliability of integrated circuit devices formed using these methods and structures can thus be increased.


REFERENCES:
patent: 3657029 (1972-04-01), Fuller
patent: 4335502 (1982-06-01), Richman
patent: 5515984 (1996-05-01), Yokoyama et al.
patent: 5567964 (1996-10-01), Kashihara et al.
patent: 5717250 (1998-02-01), Schuele et al.
patent: 5776823 (1998-07-01), Agnello et al.

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