Methods for forming patterned layers including notched etching m

Details Methods for forming patterned layers including notched etching m Methods for forming patterned layers including notched etching m

1997-09-03

2000-09-12

Brown, Peter Toby

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438 3, 438240, 438250, 438253, 438393, 438396, 438945, 438720, H01L 218242

Patent

active

061177466

ABSTRACT:
A method for patterning a layer of a microelectronic device includes the step of forming an etching mask on the layer to be etched opposite the microelectronic substrate. The etching mask defines exposed portions of the material layer and the etching mask has a notch in the sidewall thereof adjacent the material layer. The exposed portions of the material layer are then etched. More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer on the layer to be etched and forming a second patterned mask layer on the first patterned mask layer wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining the notch in the sidewall of the etching mask.

REFERENCES:
patent: 5332653 (1994-07-01), Cullen et al.
patent: 5500386 (1996-03-01), Matsumoto et al.
patent: 5515984 (1996-05-01), Yokoyama et al.
patent: 5527729 (1996-06-01), Matsumoto et al.
patent: 5658820 (1997-08-01), Chung
patent: 5930639 (1999-07-01), Schuele et al.
Won Jong Yoo et al., Control of Etch Slope During Etching of Pt in Ar/Cl.sub.2 /O.sub.2 Plasmas, Jpn. J. Appl. Phys., vol. 5, Part 1, No. 4B, Apr. 1996, pp. 2501-2504.

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