Methods for forming multiple damascene layers

Details Methods for forming multiple damascene layers Methods for forming multiple damascene layers

2003-05-28

2004-04-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S638000

Reexamination Certificate

active

06723636

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to an improved method for forming multiple damascene layers.
BACKGROUND OF THE INVENTION
Semiconductor devices are widely used in today's society. Many different types of structures may be adopted within a semiconductor device depending on the functions intended to be performed by the device. One such structure is a dual damascene structure. In forming a dual damascene structure, a trench is formed over a via so that the via may electrically couple the trench to an underlying conductor. To form a trench, the underlying via is generally filled with a polymer or other suitable material to provide a smooth surface for the deposition of the trench material. However, during the etching process to define the trench in the trench material, certain manufacturing problems may occur. For example, a protrusion, often referred to as a “fence” or a “veil,” may be formed when the trench is etched to reach the polymer material that fills the via. Further, depending on the material that is used to fill the via, nitrogen-containing compounds may diffuse through the filler material and contaminate the photoresist that may be used to pattern the trenches. This problem is often referred to as “via poisoning.”
Fences operate to increase the aspect ratio of a via, which makes the via harder to fill and decreases the reliability of the semiconductor device. Further, a fence may be bent over during the processing of the device, which makes the via difficult to fill. Any portion of photoresist that is contaminated by via poisoning cannot be patterned, which prevents a trench from being formed at the intended locations.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.
Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, reliability of a semiconductor device is increased by reducing the probability of fence formation. In another embodiment, probability of manufacturing error is reduced by preventing via poisoning. In another embodiment, the manufacturing process of a dual damascene structure is simplified.
Other technical advantages may be readily ascertained by one readily skilled in the art.


REFERENCES:
patent: 6323121 (2001-11-01), Liu et al.
patent: 6331479 (2001-12-01), Li et al.
patent: 6383919 (2002-05-01), Wang et al.
patent: 6475904 (2002-11-01), Okoroanyanwu et al.
patent: 2003/0139034 (2003-07-01), Yuang
Makarem Hussein, Sam Sivakumar, Ruth Brain, Bruce Beattie, Phi Nguyen and Mark Fradkin, “A Novel Approach To Dual Damascene Patterning”, IEEEElectron Devices Society, Intel Corporation, Portland Technology Development; (pgs. 3), 2002.

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