Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-10-23
2002-05-28
Ghyka, Alexander G. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S771000, C438S795000
Reexamination Certificate
active
06395650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming metal oxide layers within fabrications including but not limited to as microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced compositional purity, metal oxide layers within fabrications including but not limited to microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased, and more particularly as semiconductor integrated circuit microelectronic fabrication integration levels have increased, there has evolved a continuing and correlating trend towards decreased linewidth dimensions and decreased thickness dimensions of microelectronic layers that are employed when fabricating microelectronic devices and microelectronic structures employed in fabricating microelectronic fabrications.
Of the microelectronic layers whose thicknesses have traditionally decreased when fabricating advanced microelectronic fabrications, and whose thickness uniformity and materials composition integrity is generally of considerable importance when fabricating microelectronic fabrications, are capacitive dielectric layer which are conventionally employed as: (1) gate dielectric layers within field effect transistors (FETs) within semiconductor integrated circuit microelectronic fabrications; as well as (2) capacitor plate separation dielectric layers within various types of capacitors within various types of microelectronic fabrications, including but not limited to semiconductor integrated circuit microelectronic fabrications.
While continuing decreases in thickness of capacitive dielectric layers are generally desirable in the art of microelectronic fabrication in order to theoretically provide enhanced performance of capacitive devices within advanced microelectronic fabrications, there nonetheless exist considerable technical barriers to forming, with both decreased thickness and enhanced compositional Integrity, capacitive dielectric layers of conventional dielectric materials, such as silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites thereof, such as to provide enhanced performance of capacitive devices within advanced microelectronic fabrications, and in particular enhanced performance of capacitive devices within advanced semiconductor integrated circuit microelectronic fabrications.
In an effort to provide enhanced performance of capacitive devices within advanced microelectronic fabrications while avoiding decreased thicknesses of capacitive dielectric layers within the capacitive devices, there has been proposed in the alternative of employing conventional silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites thereof when forming capacitive dielectric layers within advanced microelectronic fabrication, to employ dielectric materials having generally higher dielectric constants, typically and preferably in a range of from about 10 to about 30 (in comparison with a range of from about 4 to about 8 for conventional silicon oxide dielectric materials, silicon nitride dielectric materials, silicon oxynitride dielectric materials and composites thereof). Such dielectric materials having generally higher dielectric constants allow for increased thicknesses of capacitive dielectric layers while simultaneously providing for enhanced capacitive properties of capacitive devices when fabricating microelectronic fabrications. Of the higher dielectric constant dielectric materials that have been proposed for use when forming capacitive dielectric layers within capacitive devices within advanced microelectronic fabrications, alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials (i.e., metal silicate dielectric materials), as well as derivatives thereof, are presently of considerable interest.
While alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, are thus desirable in the art of microelectronic fabrication for use when forming capacitive dielectric layers within capacitive devices within microelectronic fabrications, alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, are similarly nonetheless also not entirely without problems in the art of microelectronic fabrication when forming capacitive dielectric layers within capacitive devices within microelectronic fabrications. In that regard, it is often difficult to form alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, with enhanced compositional purity when forming a capacitive dielectric layer within a capacitive device within a microelectronic fabrication, particularly when employing for forming the alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, chemical vapor deposition (CVD) methods, and in particular chemical vapor deposition (CVD) methods that employ metal and carbon containing source materials, such as but not limited to organometallic (i.e., metal-carbon bonded) metal and carbon containing source materials.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials for forming, with enhanced compositional purity, alternative primary and higher order metal oxide dielectric materials, including metal-silicon oxide dielectric materials, and derivatives thereof, for use when forming capacitive dielectric layers within capacitive devices within microelectronic fabrications.
It is towards the foregoing object that the present invention is more specifically directed.
Various methods and materials have been disclosed within arts including but not limited to microelectronic fabrication arts, for forming substrates and layers, such as but not limited to microelectronic fabrication substrates and microelectronic fabrication layers, with desirable properties within arts including but not limited to microelectronic fabrication arts.
For example, Jelks, in U.S. Pat. No. 4,505,949, discloses a method for forming within a microelectronic fabrication a microelectronic layer upon a microelectronic substrate while avoiding when forming the microelectronic layer upon the microelectronic substrate use of an extrinsic toxic gaseous microelectronic layer source material. To realize the foregoing object, the method comprises a two step method wherein: (1) a first step within the two step method employs an in-situ upstream plasma etching of a solid microelectronic layer source material target to form an intrinsic gaseous microelectronic layer source material; and (2) a second step within the two step method employs an in-situ downstream decomposition, preferably an in-situ downstream laser initiated decomposition, of the intrinsic gaseous microelectronic layer source material, to form the microelectronic layer upon the microelectronic substrate.
In addition, Callegari et al., in “DUV stability of carbon films for attenuated phase shift mask applications,” SPIE 23
rd
Annual International Symposium on Microlithography, Santa Clara, Calif., Feb. 22-27, 1998, discloses a method for fabricating within an attenuated phase shift mask fabrication an amorphous carbon layer for use as a semitransparent shifter layer within the attenuated phase shift mask fabrication, such that the attenuated phase shift mask fabrication is stable upon deep ultraviolet irradiation within an oxygen containing ambient environment (i.e., under conventional photoexposure conditions to which the attenuated phase shift mask fa
Callegari Alessandro Cesare
Doany Fuad Elias
Gousev Evgeni Petrovich
Zabel Theodore Harold
Ghyka Alexander G.
Szecsy Alek P.
Trepp Robert M.
LandOfFree
Methods for forming metal oxide layers with enhanced purity does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for forming metal oxide layers with enhanced purity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for forming metal oxide layers with enhanced purity will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2873547