Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-10-19
2002-05-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S122000, C438S124000, C438S612000
Reexamination Certificate
active
06395582
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the packaging of integrated circuits, and more particularly to tape ball grid array (TBGA) semiconductor device packages having ground vias, and methods for manufacturing ground vias in TBGAs.
2. Description of the Related Art
The continuous increase in performance of integrated circuits is having a proportionate increase in demand for integrated circuit packages that dissipate heat more efficiently, operate under higher clock frequencies, and produce smaller footprints while meeting increased reliability requirements. There are a number of packaging technologies that offer some of these properties, but fail to meet others. Multi-layer ceramic and deposited thin film BGAs are among some of the high performance solutions commonly available today. Unfortunately, these solutions tend to be prohibitively expensive, and therefore fail to meet the highly competitive cost structure associated with high volume packaging operations. As such, the high cost of packaging materials and package manufacturing limit their use in cost sensitive high performance products.
FIG. 1
shows a prior art “cavity down” BGA package
5
having a multi-layer printed circuit board (PCB) substrate and a metal heat spreader
10
as disclosed by R. C. Marrs et al. in U.S. Pat. No. 5,583,378. In the illustrated construction, the cavity is defined by PCB interconnect metal layers
14
,
16
and
18
, which are patterned over dielectric layers
24
. In this example, the multiple layer PCB is formed by alternating layers of metal (i.e.,
14
,
16
and
18
) and dielectric layers (i.e.,
24
), which may be a BT resin dielectric available from Mitsubishi Gas & Chemical Co. of Japan. Bonding shelves
28
are defined as part of each of the patterned metal layers
14
and
16
, and are used for wire bonds
26
. In this manner, wire bonds
26
may be electrically interconnected to a semiconductor die
12
that is shown attached to the heat spreader
10
with a die attach epoxy
13
.
To complete the electrical interconnections between metal layers, a plurality of vias
30
may be used. In typical BGA designs that implement PCB technology (where the minimum metal trace width is about 100 microns), at least four metal layers are needed to interconnect about five rows of solder balls
20
, and even more metal layers are needed when power and ground planes are required. As a result, the PCB substrate alone inevitably grows to thicknesses greater than 0.7 mm, thereby substantially increasing the cost of manufacturing the packaging arrangement. Further, thicker substrates have poor heat dissipation performance and reduced package reliability. Further yet, the multiple metal layers required to complete complex circuit routing tends to increase the number of metal traces and via interconnects. Unfortunately, an increase in trace length and density typically contributes to an increase in trace inductance as well as electrical noise associated with electrical reflections. Each of these side effects represent exemplary drawbacks of a conventional packaging arrangement.
To accommodate thicker dies
12
, designers typically increase the thickness of dielectric layers, such as the dielectric layer
24
that is interposed between the heat spreader
10
and metal layer
14
. Though this serves to increase the cavity depth, the increased thickness will act to degrade heat dissipation while providing no improvement in electrical performance. Further, when die
12
is encapsulated with an encapsulant
22
and subjected to high solder reflow temperatures (i.e., 220 degrees Celsius or higher), the inherently poor heat dissipation characteristics of the packaging arrangement
5
may cause the die
12
and other package layers to delaminate. Accordingly, when heat is inadequately dissipated, the packaged arrangement will be more susceptible to over heating failures.
FIG. 2
is another example of a cavity down BGA package
50
having a “flex tape interconnect substrate”
16
attached to a heat spreader
10
as disclosed by M. Karnezos in U.S. Pat. No. 5,397,921, and hereby incorporated by reference. In this example, a cavity
15
is an integral feature of the heat spreader
10
, that is typically defined by an etching operation. A particular drawback of etching is that the side walls of cavity
15
may be quite uneven and sometimes produces pointy edges around the mouth of the cavity
15
. These pointy edges act as stress concentration points which cause cracks in the encapsulation and in turn reduce the package reliability.
The flex tape interconnect substrate
16
is attached directly to the heat spreader
10
via an adhesive
23
. In the example shown, the flex tape interconnect substrate
16
is designed such that a gold or silver plated ground ring
21
, of the heat spreader
10
, is left exposed around a cavity
15
. The plated ground ring
21
is therefore made available for wire bonds
26
″ that connect to die
12
. Other bonding wires
26
′may typically be used for interconnecting die
12
to various signal, power and ground lines that interconnect to selected solder balls
20
.
The flex tape interconnect substrate
16
also includes a first dielectric layer
25
, a single metal routing layer
18
′ and a second dielectric
36
. Typical flex tape interconnect substrates are usually custom ordered to a packaging designer's specifications from companies such as Sumitomo Metal and Mining Co. of Japan. As is well known, when complex applications demand additional signal routing to the die
12
, additional solder balls
20
will be needed, thereby requiring the flex tape interconnect substrate to have more than one metal layer. Although multi-metal flex tape interconnect substrates may be designed, the overall semiconductor package cost can potentially double with each additional metal layer.
Although the semiconductor die
12
being directly attached to the cavity
15
provides a lower heat resistive path through the heat spreader compared to the package of
FIG. 1
, the package may suffer from delamination at the interface between the die attach epoxy
13
and the heat spreader
10
. The delamination is believed to occur when cavity
15
begins to bow in response to increased temperatures produced when semiconductor die
12
is operational. In fact, because the cavity
15
bottom is only about one third the thickness of the heat spreader
10
main body, it will naturally tend to bow and differentially expand under elevated temperatures.
A number of techniques used to combat delamination include increasing the adhesion strength of the die attach epoxy
13
and encapsulation
22
to the cavity
15
surfaces. The increased adhesion is typically achieved by treating the cavity
15
surfaces with a thick metal oxide. However, applying the thick metal oxide to the cavity
15
surfaces is very expensive. In addition, the thick metal oxide is incompatible with the silver plating operations used on the one-piece heat spreader
10
, thereby requiring more expensive gold plating operations.
The encapsulation compound
22
also naturally absorbs moisture that may be confined within the cavity
15
. As is well known, when moisture is confined within encapsulated cavities, the confined moisture becomes expanding steam during subsequent solder reflow operations that range in temperatures up to 220 degrees Celsius. Naturally, the confined steam expands in an outward direction causing a well known “popcorn” cracking in the encapsulation
22
.
As such, the cost of a typical one-piece heat spreader is particularly high due to the multiple fabrication operations needed to etch the cavity
15
to a sufficient depth, and metal oxide coatings. Furthermore, because heat spreaders are typically manufactured in strips having a number of package sites, if one package site is defective, the entire strip is oftentimes scrapped in an attempt to minimize losses.
In view of the foregoing, there is a need for a tape ball grid array (TBGA) semiconducto
Karnezos Marcos
Ryu Seung Ryul
Sohn Ju Yung
Jones Josetta
Martine & Penilla LLP
Niebling John F.
Signetics
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