Methods for forming area-efficient scan chains in integrated...

Details Methods for forming area-efficient scan chains in integrated... Methods for forming area-efficient scan chains in integrated...

2008-05-20

2008-05-20

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07376915

ABSTRACT:
A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.

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Synopsys, How To Avoid MUXs in Front of Scan Segments, https://solvnet.synopsys.com, Synopsys, Inc., 2003.

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