Methods for forming and integrated circuit structures...

Details Methods for forming and integrated circuit structures... Methods for forming and integrated circuit structures...

2007-08-07

2007-08-07

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S240000

Reexamination Certificate

active

09590795

ABSTRACT:
Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

REFERENCES:
patent: 4105442 (1978-08-01), Fieberg et al.
patent: 4132569 (1979-01-01), DePablo et al.
patent: 4564702 (1986-01-01), Wennerberg
patent: 4851895 (1989-07-01), Green et al.
patent: 5068199 (1991-11-01), Sandhu
patent: 5109238 (1992-04-01), Watanabe et al.
patent: 5130885 (1992-07-01), Fazan et al.
patent: 5318920 (1994-06-01), Hayashide
patent: 5342800 (1994-08-01), Jun
patent: 5358889 (1994-10-01), Emesh et al.
patent: 5364813 (1994-11-01), Koh
patent: 5372962 (1994-12-01), Hirota et al.
patent: 5427974 (1995-06-01), Lur et al.
patent: 5466310 (1995-11-01), Ninham et al.
patent: 5608247 (1997-03-01), Brown
patent: 5612560 (1997-03-01), Chivukula et al.
patent: 5696014 (1997-12-01), Figura
patent: 5696017 (1997-12-01), Ueno
patent: 5834357 (1998-11-01), Kang
patent: 5852307 (1998-12-01), Aoyama et al.
patent: 5877063 (1999-03-01), Gilchrist
patent: 5893731 (1999-04-01), Lee et al.
patent: 5923999 (1999-07-01), Balasubramanyam et al.
patent: 5926360 (1999-07-01), Laibowitz et al.
patent: 5930584 (1999-07-01), Sun et al.
patent: 5959327 (1999-09-01), Sandhu et al.
patent: 5962065 (1999-10-01), Weimer et al.
patent: 5970309 (1999-10-01), Ha et al.
patent: 5985714 (1999-11-01), Sandhu et al.
patent: 6010931 (2000-01-01), Sun et al.
patent: 6015743 (2000-01-01), Zahurak et al.
patent: 6037220 (2000-03-01), Chien et al.
patent: 6049101 (2000-04-01), Graettinger et al.
patent: 6060351 (2000-05-01), Parekh et al.
patent: 6060367 (2000-05-01), Sze
patent: 6091099 (2000-07-01), Kiyotoshi et al.
patent: 6204203 (2001-03-01), Narwankar et al.
patent: 6218233 (2001-04-01), Takemura
patent: 6284587 (2001-09-01), Yamauchi et al.
patent: 6294807 (2001-09-01), Chittipeddi et al.
patent: 6309713 (2001-10-01), Mak et al.
patent: 6344413 (2002-02-01), Zurcher et al.
patent: 6355492 (2002-03-01), Tanaka et al.
patent: 6365502 (2002-04-01), Paranjpe et al.
patent: 6409904 (2002-06-01), Uzoh et al.
patent: 6436786 (2002-08-01), Tsuzumitani et al.
patent: 6458183 (2002-10-01), Phillips et al.
patent: 6458651 (2002-10-01), Rhodes
patent: 6635523 (2003-10-01), Uchiyama et al.
patent: 57075653 (1983-11-01), None
patent: 94057610 (1987-05-01), None
patent: 62256931 (1987-11-01), None
patent: 402197532 (1990-08-01), None
patent: 91021490 (1991-03-01), None
Kawahara, Takaaki et al., “(Ba, Sr)TiO3Films Prepared by Liquid Source Chemical Vapor Deposition on Ru Electrodes,”Jpn. J. Appl. Phys., 35:4880-4885 (1996).
Kaga et al., “Thermal Stability of RuO2Thin Films and Effects of Annealing Ambient on Their Reduction Process,”Jpn. J. Appl. Phys. 38:3689-3692 (Jun. 15, 1999).
Hayashide et al., “Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode,”Jpn. J. Appl. Phys., pp. 869-872 (1990).
Matsui et al., “Thermal Stability of a RuO2Electrode Prepared by DC Reactive Sputtering”,Jpn. J. Appl. Phys. 39:256-263 (Jan. 15, 2000).

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