Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-08-16
2011-08-16
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S786000, C257SE21590, C257SE23023
Reexamination Certificate
active
07998852
ABSTRACT:
Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
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PCT Application No. PCT/US2009/065902; Search Report and Written Opinion dated Jun. 15, 2010.
Bennett Mark A.
Burger Wayne R.
Jones Jeffrey K.
Kerr Colin
Miera Michele L.
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz P.C.
Payen Marvin
Pham Thanh V
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