Methods for forming a gate in a semiconductor device

Details Methods for forming a gate in a semiconductor device Methods for forming a gate in a semiconductor device

2005-10-18

2005-10-18

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

Reexamination Certificate

active

06955990

ABSTRACT:
Methods for forming a gate in a semiconductor device are disclosed. In an example method, the gate is formed such that the CD of an upper portion of the gate is greater than the CD of a lower portion of the gate by performing multiple etching processes. In an illustrated example, the etching processes are performed in three stages, (i.e., a first dry etching process for etching the upper portion, a second dry etching process for etching the lower portion and a third dry etching) under three different process conditions, thereby causing a sidewall profile of the gate to have a two-layered structure.

REFERENCES:
patent: 5312518 (1994-05-01), Kadomura
patent: 5880035 (1999-03-01), Fukuda
patent: 6063710 (2000-05-01), Kadomura et al.
patent: 6174408 (2001-01-01), Kadomura et al.

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