Methods for filling trenches in a semiconductor wafer

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

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438695, 438714, 438788, 20419223, H01L 21316

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active

059151900

ABSTRACT:
A method for filling a trench in a semiconductor wafer that is disposed in a plasma-enhanced chemical vapor deposition chamber. The method includes the step of depositing a protection layer of silicon dioxide over the wafer and into the trench while the wafer is biased at a first RF bias level. The protection layer has a thickness that is insufficient to completely fill the trench. Further, there is provided the step of forming a trench-fill layer of silicon dioxide over the protection layer and into the trench while the wafer is biased at a second RF bias level that is higher than the first bias level.

REFERENCES:
patent: 4401054 (1983-08-01), Matsuo et al.
patent: 4476622 (1984-10-01), Cogan
patent: 4681653 (1987-07-01), Purdes
patent: 4732761 (1988-03-01), Machida et al.
patent: 4839306 (1989-06-01), Wakamatsu
patent: 4894311 (1990-01-01), Uenishi et al.
patent: 4952274 (1990-08-01), Abraham
patent: 5089442 (1992-02-01), Olmer
patent: 5182221 (1993-01-01), Sato
patent: 5252520 (1993-10-01), Kocmanek et al.
patent: 5286518 (1994-02-01), Cain et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5562952 (1996-10-01), Nakahigashi et al.
patent: 5679606 (1997-10-01), Wang et al.
patent: 5753564 (1998-05-01), Fukada
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, (No month 1990) pp. 194-196.
Wolf, Stanley & Richard Tauber, Silicon Processing for the VLSI Era, vol. 1, pp. xxii and 167 (1986) No month.
R.C. Jaeger, Chapter 2: "Isolation Technologies for Integrated Circuits," Introduction to Microelectronic Fabrication, 1988. No Month.
A, Bryant, W. Hansch and T. Mii, "Characteristics of CMOS Device Isolation for the ULSI Age," Siemens Components, Inc., 1994 IEEE. No Month.
S. Wolf, "A Review of IC Isolation Technologies--Parts 1-9," Solid State Technology, Mar. 1992-Jun. 1993.
S.M. Rossnagel, "Directional and preferential sputtering-basedphysical vapor deposition," Thin Solid Films, vol. 263, No. 1, Jul. 1, 1995, pp. 1-12, IBM Research, Yorktown Heights, NY.
M. Gross and C.M. Horwitz, "Silicon dioxide trench filling process in a radio-frequency hollow cathode reactor," Journal of Vacuum Science and Technology, Part B, vol. 11, No. 2, Mar. 1, 1993, pp. 242-248, NY.
K. Machida and H. Oikawa, A High Aspect Ratio and High Throughput SiO.sub.2 Planarization Technology with Bias-ECR Plasma Deposition, Symposium on VLSI Technology, May 18-21, 1987, No. SYMP. 7, May 18, 1987, Inst. Of Electrical Engineers, pp. 69-70, IEEE Electron Devices Society.

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