Methods for fabricating three dimensional integrated circuits

Details Methods for fabricating three dimensional integrated circuits Methods for fabricating three dimensional integrated circuits

2006-06-20

2006-06-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S152000, C438S165000, C438S200000

Reexamination Certificate

active

07064018

ABSTRACT:
A method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating a common interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

REFERENCES:
patent: 5563526 (1996-10-01), Hastings et al.
patent: 5581501 (1996-12-01), Sansbury et al.
patent: 5625221 (1997-04-01), Kim et al.
patent: 5679967 (1997-10-01), Janai et al.
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 5943574 (1999-08-01), Tehrani et al.
patent: 5949710 (1999-09-01), Pass et al.
patent: 6018476 (2000-01-01), Madurawe et al.
patent: 6097211 (2000-08-01), Couts-Martin et al.
patent: 6121961 (2000-09-01), Feldman
patent: 6134173 (2000-10-01), Cliff et al.
patent: 6242767 (2001-06-01), How et al.
patent: 6331784 (2001-12-01), Mason et al.
patent: 6331789 (2001-12-01), Or-Bach
patent: 6448808 (2002-09-01), Young et al.
patent: 6504742 (2003-01-01), Tran et al.
patent: 6515511 (2003-02-01), Sugibayashi et al.
patent: 6569717 (2003-05-01), Murade
patent: 6582980 (2003-06-01), Feldman et al.
patent: 6613611 (2003-09-01), How et al.
patent: 6627985 (2003-09-01), Huppenthal et al.
patent: 2001/0003428 (2001-06-01), Or-Bach
patent: 2001/0047509 (2001-11-01), Mason et al.
patent: 2003/0023762 (2003-01-01), Dhir et al.
Ashok K. Sharma, “Programmable Logic Handbook—PLDs, CPLDs, & FPGAs”, 1998, pp. 99-171, McGraw-Hill, USA.

Affiliated with

Also associated with

Rating

Methods for fabricating three dimensional integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for fabricating three dimensional integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating three dimensional integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3679470