Methods for fabricating semiconductor structures

Details Methods for fabricating semiconductor structures Methods for fabricating semiconductor structures

2007-01-22

2010-11-30

Menz, Laura M (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S270000, C438S187000

Reexamination Certificate

active

07842616

ABSTRACT:
Methods for fabricating semiconductor structures are provided. A first layer may be deposited onto a substrate followed by the deposition of a second layer onto the first layer. A plurality of line structures may be etched in the second layer. A third layer, deposited onto the plurality of line structures of the second layer, may subsequently be etched to expose the plurality of line structures in the second layer. The plurality of line structures in the second layer may be removed, leaving an etched third layer. The etched third layer may be used as a mask to etch the first layer to form a semiconductor structure in the first layer. In some respects, the methods may include steps for etching the substrate using the etched first layer. The methods may also provide annealing the etched substrate to form a corrugate substrate surface.

REFERENCES:
patent: 6063688 (2000-05-01), Doyle et al.
patent: 6667237 (2003-12-01), Metzler
patent: 6706597 (2004-03-01), Geusic et al.
patent: 6825087 (2004-11-01), Sharp et al.
patent: 6967140 (2005-11-01), Doyle
patent: 7190050 (2007-03-01), King et al.
patent: 7265008 (2007-09-01), King et al.
patent: 7285466 (2007-10-01), Kim et al.
patent: 7508031 (2009-03-01), Liu et al.
patent: 7605449 (2009-10-01), Liu et al.
patent: 2003/0219948 (2003-11-01), Kuribayashi
patent: 2004/0191980 (2004-09-01), Rios et al.
patent: 2006/0151830 (2006-07-01), Gonzalez
patent: 2006/0276032 (2006-12-01), Arakawa et al.
patent: 2007/0001237 (2007-01-01), King et al.
patent: 2007/0004113 (2007-01-01), King et al.
patent: 2007/0120156 (2007-05-01), Liu et al.
patent: 2007/0122953 (2007-05-01), Liu et al.
patent: 2007/0122954 (2007-05-01), Liu et al.
patent: 2007/0128782 (2007-06-01), Liu et al.
patent: 2008/0176406 (2008-07-01), Ikeda et al.
patent: 2009/0269916 (2009-10-01), Kang et al.
patent: 2009/0269918 (2009-10-01), Ma et al.
patent: WO 2006/101695 (2006-09-01), None
PCT International Search Report and Written Opinion, issued in International Application No. PCT/US2007/060865, dated Jan. 17, 2008.
Kuribayashi et al., “Hydrogen pressure dependence of trench corner rounding during hydrogen annealing,”J. Vac. Sci. Technol., 22:1406-1409, 2004.
Nasrullah et al., “An edge-defined nano-lithography technique suitable for low thermal budget process and 3-D stackable devices,”2003 Third iEEE Conference on Nanotechnology, Proceedings, 2:502-505, 2003.

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