Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-26
2004-01-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S301000, C438S962000
Reexamination Certificate
active
06673717
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic devices and fabrication methods and systems therefor, and more particularly to single-electron devices and fabrication methods and systems therefor.
BACKGROUND OF THE INVENTION
Single-Electron Transistor (SET) devices and fabrication methods and systems are being widely investigated for high density and/or high performance microelectronic devices. As is well known to those having skill in the art, single-electron transistors use single-electron nanoelectronics that can operate based on the flow of single-electrons through nanometer-sized particles, also referred to as nanoparticles, nanoclusters or quantum dots. Although a single-electron transistor can be similar in general principle to a conventional Field Effect Transistor (FET), such as a conventional Metal Oxide Semiconductor FET (MOSFET), in a single-electron transistor, transfer of electrons may take place based on the tunneling of single-electrons through the nanoparticles. Single-electron transistors are described, for example, in U.S. Pat. Nos. 5,420,746; 5,646,420; 5,844,834; 6,057,556 and 6,159,620, and in publications by the present inventor Brousseau, III et al., entitled
pH
-
Gated Single
-
Electron Tunneling in Chemically Modified Gold Nanoclusters
, Journal of the American Chemical Society, Vol. 120, No. 30, 1998, pp. 7645-7646, and by Feldheim et al., entitled
Self
-
Assembly of Single
-
electron Transistors and Related Devices, Chemical
Society Reviews, Vol. 27, 1998, pp. 1-12, and in a publication by Klein et al., entitled
A Single
-
Electron Transistor Made From a Cadmium Selenide Nanocrystal
, Nature, 1997, pp. 699-701, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
A major breakthrough in single-electron transistor technology is described in U.S. patent application Ser. No. 09/376,695, entitled
Sensing Devices Using Chemically
-
Gated Single
-
electron Transistors
, by Daniel L. Feldheim and the present inventor Louis C. Brousseau, III, also published as International Publication No. WO 01/13432 A1, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein. Described therein is a chemically-gated single-electron transistor that can be adapted for use as a chemical or biological sensor. Embodiments of these chemically-gated single-electron transistors include source and drain electrodes on a substrate and a nanoparticle between the source and drain electrodes, that has a spatial dimension of a magnitude of approximately 12 nm or less. An analyte-specific binding agent is disposed on a surface of the nanoparticle. A binding event occurring between a target analyte and the binding agent causes a detectable change in the characteristics of the single-electron transistor.
Other single-electron devices, including but not limited to resonant tunneling diodes and nonvolatile memory cells, also are being investigated. However, it may be difficult to fabricate single-electron devices using conventional photolithography that is employed to fabricate microelectronic devices. For example, in order to provide quantum mechanical effects with nanoparticles, it may be desirable to provide spacing between the source and drain electrodes of a single-electron transistor that is less than about 20 nm, or less than about 12 nm or about 10 nm. It also may be desirable to accurately place one or more nanoparticles with respect to this spacing. It may be difficult, however, to provide these spacings and/or to place these nanoparticles using conventional lithography at low cost and/or with acceptable device yields.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide methods and systems for fabricating nanopores for single-electron devices and single-electron devices that include nanopores. The nanopores may be used as templates for placing of a desired number and/or type of nanoparticles at a desired location in the devices.
More specifically, single-electron devices may be fabricated, according to some embodiments of the present invention, by providing on a substrate, a plurality of spaced apart electrode regions, a spacer region therebetween, and a cover layer on the spaced apart electrode regions and on the spacer region. A wet etching solution is contacted to the cover layer. At least one of the spaced apart electrode regions is energized, to selectively wet etch the cover layer adjacent the spacer region and define a nanopore in the cover layer adjacent the spacer region. At least one nanoparticle is placed in the nanopore. In some embodiments, the spacer region is less than about 20 nm thick, and the nanopore is less than about 20 nm wide. In other embodiments, the nanopore is about 10 nm wide and about 10 nm thick. Accordingly, some embodiments of the present invention can allow small dimensioned nanopores to be aligned to a buried spacer region.
In some embodiments of the invention, the etching solution is an acid or a base. In other embodiments, the base is a weak base solution having a pH of less than about 14. In yet other embodiments, the weak base solution comprises an amine. In still other embodiments, the weak base solution comprises ethylene diamine and/or triethylamine. In other embodiments, the acid is sulfuric acid and/or phosphoric acid. Other acidic or basic etching solutions may be used.
Still other embodiments provide a counter electrode that is adjacent and spaced apart from the spacer regions and contact the wet etching solution to the cover layer and to the counter electrode. At least one of the spaced apart electrode regions and the counter electrode is energized to selectively wet etch the cover layer adjacent the spacer region and define the nanopore in the cover layer adjacent the spacer region. In other embodiments, the counter electrode and at least one of the spaced apart electrode regions are energized by applying a Direct Current (DC) voltage therebetween. In yet other embodiments, an Alternating Current (AC) voltage is used.
In some embodiments of the present invention, the plurality of spaced apart electrode regions and the spacer region therebetween may be provided on a substrate using conventional photolithography techniques. Other embodiments of the invention can provide a plurality of spaced apart electrode regions and a spacer region therebetween using methods and structures that are described in application Ser. No. 09/905,319, to Brousseau, III, filed Jul. 13, 2001, and entitled
Single
-
Electron Transistors and Fabrication Methods in Which the Thickness of An Insulating Layer Defines Spacing Between Electrodes
, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. In particular, in some of these embodiments, a first electrode is formed on the substrate. An insulating layer is conformally formed on the first electrode. A second electrode is conformally formed on the insulating layer opposite the first electrode, such that the first electrode and the second electrode define the plurality of spaced apart electrode regions and the insulating layer therebetween defines the spacer region. Still other embodiments can provide the plurality of spaced apart electrode regions and the spacer region therebetween using structures and methods that are described in application Ser. No. 09/905,471, to Brousseau, III, filed Jul. 13, 2001, and entitled
Single
-
Electron Transistors and Fabrication Methods in Which a Projecting Feature Defines Spacing Between Electrodes
, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. In some of these embodiments, a projecting feature is formed on a substrate that projects from a face thereof. A first electrode is formed on the projecting feature. A second electrode is formed on the projecting feature and is spaced apart from the first electrode, such that the first electrode and the second electrode define the plurality of spaced ap
Lindsay Jr. Walter L.
Myers Bigel & Sibley & Sajovec
Quantum Logic Devices, Inc.
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