Methods for fabricating MOS transistors with notched gate...

Details Methods for fabricating MOS transistors with notched gate... Methods for fabricating MOS transistors with notched gate...

2002-11-12

2004-11-02

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S259000, C438S199000, C438S201000, C438S202000, C438S221000, C438S299000, C438S303000, C438S304000, C257S069000, C257S204000

Reexamination Certificate

active

06812111

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2002-05052, filed on Jan. 29, 2002, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices and, more particularly, to methods for fabricating MOS transistors with notched gate electrodes.
2. Background of the Invention
As semiconductor devices become increasingly integrated, the area occupied by MOS transistors on integrated circuits has been gradually reduced. As the channel length of a MOS transistor decreases, there may arise a short channel effect (SCE), which seriously deteriorates the characteristics of the transistor. The SCE is caused by the phenomena of drain-induced barrier lowering (DIBL), punchthrough, hot carriers, and the like.
As the space between a source and drain decreases, electrons emitted from the source are sharply accelerated due to a high electric field in the vicinity of the edge of the drain junction region, which generates hot carriers, in turn causing characteristics of semiconductor devices to be degraded. The foregoing phenomenon is typically referred as the hot carrier effect. For this reason, MOS transistors of lightly doped drain (LDD) structures have been extensively used to improve degradation caused by the hot carriers.
FIG. 1
is a cross-sectional view of a MOS transistor of a conventional LDD structure.
Referring to
FIG. 1
, a device isolation layer
105
is formed in a semiconductor substrate
100
to define an active region. A gate stack, which includes a gate insulation layer
110
, a gate electrode
115
, and a gate spacer
125
, is formed on the active region. A lightly doped impurity region
120
and a heavily doped impurity region
130
are formed in the semiconductor substrate of both edges of the gate insulation layer
110
. The lightly doped and heavily doped impurity regions
120
and
130
correspond to source and drain regions.
In the LDD structure, the lightly doped impurity region
120
self-aligned to the gate electrode
115
is disposed between a channel region and the heavily doped impurity region
130
. The lightly doped impurity region
120
allows an electric field between the drain and channel regions to be reduced such that, even if a high voltage is applied to the drain region, carriers emitted from the source region are not sharply accelerated. As a result, adverse effects due to the hot carrier effect can be mitigated.
However, since parasitic capacitance, which is exhibited in the overlapped region of the gate electrode and the LDD region, reduces speed of devices, the LDD structure makes it difficult to realize a MOS transistor suitable for high-speed operation. To improve performance lowered by the LDD structure, MOS transistors with notched gate electrodes have been recently proposed.
FIG. 2
is a cross-sectional view of a MOS transistor with a notched gate electrode.
Referring to
FIG. 2
, a device isolation layer
205
is formed at a semiconductor substrate
200
to define an active region. A gate stack, which includes a gate insulation layer
210
, a notched gate electrode
215
, and a gate spacer
225
, is formed on the active region. A lightly doped impurity region
220
and a heavily doped impurity region
230
are formed in the semiconductor substrate of both edges of the gate insulation layer
210
. The lightly doped and heavily doped impurity regions
220
and
230
correspond to source and drain regions.
One of advantages of the notched gate electrode is that the channel length is substantially reduced by a notch region
235
formed under the gate electrode. This results in reduction of overlap capacitance between the gate and the source and between the gate and the drain. Therefore, transistors may be improved in their performance and speed.
In addition, since halo implantation is the technique used for ion implantation in the substrate including a notched gate electrode, this makes it possible to form a relatively deeper ion implantation region, as compared with a conventional gate electrode. Halo implantation is thus more effective in stopping punchthrough. According to halo implantation, the notch region
235
under the edge of the gate electrode does not inhibit the ion implantation.
Finally, the notched gate electrode is a T-shaped gate, the lower portion of which may have a shorter length than the upper portion. This permits silicide to be widely formed on the upper portion of the gate electrode, thus enabling lower resistance.
A conventional method for fabricating a notched gate electrode comprises patterning a gate electrode using photolithographic and etching processes through a specific etching method in order to form a notch region under an edge of the gate electrode. For example, after forming a gate conductive layer having a stacked structure of silicon germanium and polysilicon, an etching process is performed using a difference in etch rate to form the notched gate electrode. That is, the notched gate electrode is formed using the difference in etch rate between silicon germanium and polysilicon.
The problem of the conventional method is that it is difficult to realize the notch region at a desired size. In other words, a gate electrode cannot be readily formed to a desired length. In addition, in the dry etching process for forming the gate electrode, a plasma gas may transform the gate electrode and cause an electric charge to be generated in the gate electrode. This may lead to partial concentration of an electric field or a trap charge, thus lowering reliability of the gate insulation layer.
SUMMARY OF THE INVENTION
In addressing the aforementioned limitations, the present invention provides methods for fabricating MOS transistors with notched gate electrodes, which can form a gate pattern without the need for etching the gate conductive layer and, in this manner, provides enhanced control over the resulting width and a height of the notch region.
In accordance with broad aspects of the present invention, provided is a method for fabricating a MOS transistor with a notched gate electrode that comprises forming a multi-layered insulation layer including at least two insulation layers on a substrate. The multi-layered insulation layer is patterned to form an opening exposing a predetermined region of the substrate. The opening has a stair-shaped sidewall such that an upper portion of the opening is wider than a lower portion thereof. A gate insulation layer is then formed on the exposed substrate, and a gate electrode is formed on the insulation layer to fill the stair-shaped opening. The multi-layered insulation layer is then removed. As a result, a notched gate electrode, in which a notch region is formed under an edge of the gate electrode, is formed.
Forming the opening having the stair-shaped sidewall comprises forming upper and lower openings. After forming a multi-layered insulation layer including lower and upper molding layers, the upper molding layer is etched by using a mask pattern to form the upper opening. A self-aligned spacer is then formed on a side of the upper opening. By using the self-aligned spacer as an etch mask, the lower molding layer is etched to form the lower opening. This results in formation of the opening with a stair-shaped sidewall in which the upper opening is wider than the lower opening.
Another method for forming the opening with a stair-shaped sidewall employs photolithographic and etching processes twice. In other words, after forming a multi-layered insulation layer, which includes lower and upper molding layers, the photolithography and etching are performed into the upper molding layer by using a first mask pattern to form an upper opening. Thereafter, the lower molding layer is etched using a second mask pattern so as to form the opening with a stair-shaped sidewall in which the upper opening is wider than the lower opening.


REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
patent: 6204133 (2001-03-01), Yu et al.
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