Methods for fabricating integrated circuit capacitor...

Details Methods for fabricating integrated circuit capacitor... Methods for fabricating integrated circuit capacitor...

1999-04-09

2001-01-09

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000

Reexamination Certificate

active

06171926

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit fabrication methods and more particularly to methods of fabricating integrated circuit capacitor electrodes.
BACKGROUND OF THE INVENTION
Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon and thereby store data. As the integration density of DRAM devices continues to increase, it is desirable to maintain sufficiently high storage capacitance while decreasing the area of the integrated circuit substrate that is occupied by each capacitor.
When the integration density of the integrated circuit capacitors is increased, it may become more difficult to align the capacitor lower electrode, also referred to as a storage node, to an underlying contact hole. Moreover, in order to allow relatively high capacitance while decreasing the substrate surface area of the capacitor, the height of the storage node may increase as the area decreases. For example, the height of the storage node may increase to one micron or more in a stacked capacitor structure. This may result in a high aspect ratio of the storage node, for example, an aspect ratio exceeding
5
. This high aspect ratio may make it difficult to pattern a thick conductive layer to form the storage nodes.
FIGS. 1 and 2
are cross-sectional views of DRAM cell capacitors which are fabricated by conventional methods, respectively taken along the word line direction and along the bit line direction of the DRAM device. As shown in
FIGS. 1 and 2
, a plurality of field effect transistors
3
are formed in an integrated circuit substrate
2
such as a monocrystalline silicon substrate. The field effect transistors
3
include insulated gate electrodes
7
with an insulating sidewall and capping layer
9
thereon. A plurality of spaced-apart source/drain regions
5
are also included in the integrated circuit substrate
2
. Contact pads
4
are connected to respective source/drain regions
5
. A first insulating layer such as a first oxide layer
6
is formed on the integrated circuit substrate
2
and a plurality of conductive lines such as bit lines
8
are formed thereon. A second insulating layer such as a second oxide layer
10
is formed on the first oxide layer
6
and on the bit lines
8
.
A plurality of contact openings
11
are formed in the second and first oxide layers
10
and
6
to expose the contact pads
4
. A conductive layer, preferably comprising polysilicon, is formed on the second oxide layer
10
including in the contact openings
11
at a thickness that determines the height of the storage node. An antireflective layer
13
is formed on the polysilicon layer in order to increase photolithographic resolution. The photoresist layer is formed on the antireflective layer
13
and patterned.
Using the patterned photoresist
14
, the antireflective layer
13
and the polysilicon layer are anisotropically etched, for example using plasma etching gas containing sulfur hexafluoride (SF
6
) and nitrogen (N
2
) to form storage nodes
12
. As is well known to those having skill in the art, an overetching process, for example using chlorine and nitrogen gas may be used during the step of etching a very tall polysilicon layer (for example about 10,000 Ångstroms in thickness) so as to obtain etching uniformity.
Unfortunately, during etching of the storage nodes
12
, lateral etching may also occur, especially during the overetching process, which may cause a storage node to break. More specifically, as the etching process continues to expose the upper surface of the second oxide layer
10
, the exposed surface of the second oxide layer
10
may be charged by ions of the etching gases, i.e., SF
6
+
, Cl
2
+
, and N
2
+
, due to the large etch selectivity between the polysilicon layer and the underlying oxide layer
10
. Therefore, etching ions that flow downstream in the direction of arrows
17
during the overetching process may be repelled by the charged oxide surface, thereby shifting the etching direction laterally towards the bottom sidewalls of the storage nodes
12
as shown by arrows
17
. Therefore, the bottom sidewalls of the storage node may become etched due to shifting in etching direction as shown at reference numeral
18
. Moreover, if misalignment occurs, the lateral and/or vertical overetching of the storage node may attack the misaligned portion and cause the storage node to break or become unduly thin.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of fabricating integrated circuit capacitor lower electrodes.
It is another object of the present invention to provide integrated circuit capacitor lower electrode fabrication methods that can reduce lateral etching of the electrodes during patterning thereof.
It is still another object of the present invention to provide methods of fabricating integrated circuit capacitor lower electrodes that can allow adequate alignment margins to be present during fabrication.
It is yet another object of the present invention to provide methods of fabricating integrated circuit capacitor lower electrodes that can reduce breakage of the lower electrodes during fabrication thereof.
These and other objects are provided, according to the present invention, by forming a buffer layer comprising material that is different from the second insulating layer, on the second insulating layer. The buffer layer preferably comprises material that has lower reflectivity than that of the second insulating layer and also preferably comprises material that has an etch rate for a predetermined etchant, that is intermediate that of the second insulating layer and the conductive layer of the lower. electrode. Accordingly, the buffer layer can reduce the formation of ions therein during plasma etching and thereby reduce, and preferably prevent, lateral etching of the integrated circuit capacitor lower electrodes at the base thereof Alignment margins may thereby be increased and breaking of the storage node may be reduced and preferably prevented.
More specifically, integrated circuit capacitor lower electrodes are fabricated by forming a plurality of spaced-apart contact pads on an integrated circuit substrate. A first insulating layer is formed on the integrated circuit substrate including on the contact pads. A plurality of spaced-apart conductive lines is formed on the first insulating layer, that are laterally offset from the plurality of spaced-apart contact pads. A second insulating layer is formed on the first insulating layer including on the conductive lines. A buffer layer comprising material that is different from the second insulating layer, is formed on the second insulating layer. Openings are formed that extend through the buffer layer, through the second insulating layer and into the first insulating layer between the conductive lines to expose the contact pads. A conductive layer is formed in the openings and on the buffer layer. The conductive layer is etched between the openings to form the capacitor lower electrodes.
The buffer layer preferably comprises material that has lower reflectivity than that of the second insulating layer and also preferably comprises material that has an etch rate for a predetermined etchant, that is intermediate that of the second insulating layer and the conductive layer. The first and second insulating layers preferably comprise silicon dioxide, the buffer layer preferably comprises at least one of silicon nitride and silicon oxynitride and the conductive layer preferably comprises polysilicon. During etching, a polymer preferably is formed on the capacitor lower electrode sidewalls adjacent the buffer layer. The etchant preferably is a plasma etchant including sulfur hexafluoride, chlorine and/or nitrogen gases.
Prior to forming the spaced-apart contact pads, a plurality of spaced-apart source/drain regions may be formed in the integrated circuit substrate, and

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