Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-24
2003-10-07
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S623000, C438S624000, C438S629000, C438S637000
Reexamination Certificate
active
06630395
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to electrical testing of circuits and more particularly to facilitating electrical probing by forming electrical connections to semiconductor structures incorporating low-k dielectric inter level materials.
BACKGROUND
The electrical characteristics of low-k dielectric materials make them desirable in the manufacture of semiconductor chips having sub micron features. Low-k dielectric materials include such commercial products as Dow Corning's SiLK™ and porous SiLK™, Applied Materials' Black Diamond™, Motorola's Black Diamond™ Texas Instrument's Coral™, and TSMC's Black Diamond™ and Coral™ and other organic polymers, porous oxides and carbon-doped oxides as described below. In one particular application of interest with respect to the present invention, these low-k dielectric materials are used to insulate sub-micron copper interconnects. The electrical characteristics of these low-k materials diminish the capacitive effects between the closely spaced electrical conductors. Such conductors include, for example, dual damascene-formed copper conductors used to make back-end-of-line (BEOL), multilevel electrical connections to silicon devices such as transistors.
These low-k dielectric materials, however, possess certain chemical and mechanical characteristics that make them problematic for certain applications. They are, for example, soft, pliable and porous as well as prone to electrical leakage. These characteristics make it difficult to probe through these materials to test the electrical characteristics of the underlying components. Processes typically used to open vias through the low-k dielectric materials, such as mechanical unlayering, reactive ion etching (RIE), focused ion beam (FIB) techniques and wet chemical removal processes either compromise the underlying structures to be tested or cause conductive leakage paths within the dielectric layers themselves, compromising sensitive electrical measurements.
It thus is difficult to electrically probe and analyze the electrical operating characteristics or fault characteristics of semiconductor devices fabricated using these low-k dielectric materials.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide methods and structures for providing electrical connections to and hence enabling the electrical probing of conductors, semiconductor devices, structures and other features fabricated including low-k inter level dielectric materials.
In accordance with one embodiment of the invention, there is provided a method of providing electrical contacts to an insulated device structure comprising the steps of: providing a device including at least one buried conductor overlaid by a low-k dielectric layer; etching said low-k dielectric layer to leave a cap over said buried conductor; depositing a high-k dielectric layer over said cap; forming a via through said high-k dielectric layer and said cap to expose said buried conductor; passivating the sidewall of said via; and providing a conductor through said via to make electrical contact to said buried conductor.
In accordance with another embodiment of the invention, there is provided a semiconductor structure comprising: a buried semiconductor device; a first conductor overlying said semiconductor device and connected to said semiconductor device; a low-k dielectric layer surrounding said first conductor; a low-k dielectric cap overlying said first conductor; a high-k insulator layer deposited over said low-k dielectric cap; a via through said high-k insulator layer and said low-k dielectric cap exposing a surface of said first conductor; a passivating film of high-k dielectric insulator over the wall of said via; and a second conductor extending through said via over said passivating film to contact said first conductor.
REFERENCES:
patent: 6514881 (2003-02-01), Coffman
Kane Terence Lawrence
Tenney Michael P.
International Business Machines - Corporation
Magee Thomas
Thomas Tom
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