Methods for fabricating a stress enhanced MOS transistor

Details Methods for fabricating a stress enhanced MOS transistor Methods for fabricating a stress enhanced MOS transistor

2006-10-25

2009-10-13

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S595000, C257SE21444

Reexamination Certificate

active

07601574

ABSTRACT:
Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.

REFERENCES:
patent: 7071529 (2006-07-01), Miyagawa et al.
patent: 7358551 (2008-04-01), Chidambarrao et al.
patent: 7439120 (2008-10-01), Pei
patent: 7462522 (2008-12-01), Chidambarrao et al.

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