Methods for electrically isolating portions of wafers

Details Methods for electrically isolating portions of wafers Methods for electrically isolating portions of wafers

2006-10-03

2006-10-03

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S424000

Reexamination Certificate

active

07115505

ABSTRACT:
Systems for electrically isolating portions of wafers are provided. A representative system includes a first wafer and a first conductor formed at least partially through the first wafer. A first conductor insulating layer is formed at least partially through the first wafer. The first conductor insulating layer engages the first conductor and is disposed between the first conductor and material of the first wafer. A first outer insulating layer also is provided that is formed at least partially through the first wafer. The first outer insulating layer is spaced from the first conductor insulating layer. Both the first conductor insulating layer and the first outer insulating layer are formed of dielectric material. Methods also are provided.

REFERENCES:
patent: 3663308 (1972-05-01), Davey
patent: 3769562 (1973-10-01), Bean
patent: 5998292 (1999-12-01), Black et al.
patent: 6395630 (2002-05-01), Ahn et al.
patent: 2003/0207566 (2003-11-01), Forbes et al.
patent: WO 01/65598 (2001-09-01), None
Park, T., et al., “Double Trench Isolation (DTI): A Novel Isolation Technology for Deep-Submicron Silicon Devices,” Advanced Technology Center, Samsum Electronics, Co. Ltd.

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