Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-10
2003-02-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06526562
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to processes for developing an integrated circuit design, including the development of a chip model, chip verification tools and application software.
BACKGROUND OF THE INVENTION
Current very-large-scale integrated circuits, such as central processing units (CPUs) and digital signal processors (DSPs), have extremely high complexity and extremely high operating speeds. For example, current chips may incorporate on the order of 30 million devices and may operate at speeds on the order of 1 GHz or greater. Trends in such chips are toward even greater complexities and higher operating speeds. Additional trends are toward smaller device features and larger chip areas. As may be expected, the functionality of such chips is also extremely complex.
Not surprisingly, the development of such integrated circuits is also extremely complex and may involve a large team of architects and chip developers. The development of the chip itself involves specifying the detailed functions to be performed, defining an instruction set, addressing issues of floor-planning and layout, addressing signal timing issues, and addressing power consumption issues, to name only a few. The development also involves designing software tools, such as assemblers, linkers, and the like, for use with the chip, and designing verification tools that permit the functioning of the chip to be verified. In the case of such complex chips, verification may involve billions of distinct states. The chip is typically modeled in software to permit design verification and simulation. The software model is then utilized to produce a chip layout. The coordination of these activities is extremely complex and, if done improperly or inefficiently, can result in a lengthy development process and/or an unsuccessful product.
In some cases, the development of integrated circuits is a joint effort by two or more companies. The result of the joint development effort is a chip design which can be utilized by each company in different products. However, in the case where each company is involved in the development and manufacturing of integrated circuits, each company is likely to have processes, designs and other information which it considers to be proprietary. In this situation, it is desirable to organize the chip development effort in a manner which produces the desired chip design but which does not compromise the proprietary information of the participating companies.
In some cases, the chip design may be utilized as a component in a larger integrated circuit, such as a system on a chip (SOC). For example, the chip design may represent a computation core which can be incorporated into a digital signal processor or into a special purpose chip. In this situation, the chip design preferably is in a form which is easily incorporated into the design of the SOC.
Accordingly, there is a need for methods for developing integrated circuits in an efficient and cost effective manner.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method is provided for developing an integrated circuit chip design. The method comprises the steps of (a) developing an architecture specification defining functions of the chip, (b) developing a microarchitecture specification for the chip based on the architecture specification, (c) developing a functional and structural model of the chip based on the microarchitecture specification, (d) designing software tools for use with the chip based on the architecture specification, (e) designing chip verification tools based on the microarchitecture specification, and (f) performing steps (c), (d) and (e) concurrently.
Each of steps (c), (d) and (e) may include a planning phase, a building block development phase and an execution phase. Each of the phases may have defined dependencies and defined deliverables.
The method may further include the step of developing an information database containing information on the development of the chip. The information database may include project tracking information and revision control information, and may be web-based for access by team members.
The chip verification tools may be used to verify the functional and structural model of the chip. The chip verification tools may be used iteratively following modifications to the functional and structural model of the chip. A chip layout may be synthesized to assist in developing the functional and structural model of the chip.
According to another aspect of the invention, a method is provided for developing an integrated circuit chip. The method comprises the steps of developing a chip model defining the functional and structural characteristics of the chip using information shared by first and second development entities, and implementing a chip design based on the chip model and using process and layout information which is proprietary to the first development entity and which is not shared with the second development entity.
REFERENCES:
patent: 6321329 (2001-11-01), Jaggar et al.
patent: 6343358 (2002-01-01), Jagger et al.
Onder et al, “Automatic Generation Of Micriarchitecture Simulators,” IEEE, May 14, 1998, pp. 1-10.*
Biswas et al, “Funtional Verification Of The Superscalar SH-4 Microprocessor,” IEEE, 1997, pp. 115-120.*
Bechem et al, “An Integrated Functional Performance Simulator,” IEEE, Jun. 1999, pp. 26-35.*
Shen et al, “Using Term Rewriting Systems To Design And Verify Processors,” IEEE, Jun. 1999, pp. 36-46.
Anderson William C.
Haddad Elie
Monaco James
Tomazin Thomas
Analog Devices Inc.
Siek Vuthe
Wolf Greenfield & Sacks P.C.
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