Methods for designing a product chip a priori for design...

Details Methods for designing a product chip a priori for design... Methods for designing a product chip a priori for design...

2011-02-22

2011-02-22

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07895545

ABSTRACT:
A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

REFERENCES:
patent: 7194706 (2007-03-01), Adkisson et al.
patent: 2004/0025123 (2004-02-01), Angilivelil
patent: 2005/0081130 (2005-04-01), Rinderknecht et al.
patent: 2006/0259885 (2006-11-01), Mortensen et al.
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patent: 2007/0136714 (2007-06-01), Cohn et al.
patent: 2009/0132976 (2009-05-01), Desineni et al.

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