Methods for automatically generating assertions

Details Methods for automatically generating assertions Methods for automatically generating assertions

2011-04-12

2011-04-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

Reexamination Certificate

active

07926020

ABSTRACT:
One embodiment of the present invention provides a method that automatically generates assertions of a hardware design. The method includes accessing a trace and a set of predicates of the hardware design. Then, the trace is projected over the set of predicates to generate a second trace. Then, a new set of states of the second trace is computed and the result is represented as a logical formula. The formula is reduced by logic optimization techniques. And finally, a set of logical consequences of the logic formula is produced and each logical consequence is enumerated as an assertion.

REFERENCES:
patent: 2003/0115562 (2003-06-01), Martin et al.
patent: 2005/0198597 (2005-09-01), Zhu et al.
patent: 2005/0229044 (2005-10-01), Ball
patent: 2007/0074152 (2007-03-01), Roe

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