Methods for accessing coincident cache with a bit-sliced archite

Details Methods for accessing coincident cache with a bit-sliced archite Methods for accessing coincident cache with a bit-sliced archite

1997-11-13

1999-11-23

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711129, 711154, 711157, 36518902, 36523002, G06F 1202, G06F 1208, G06F 1300

Patent

active

059918535

ABSTRACT:
A "bit-sliced" construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values, processor operations and invalidation operations can be "overlapped", and even operate simultaneously.

REFERENCES:
patent: 4370710 (1983-01-01), Kroft
patent: 4381541 (1983-04-01), Baumann et al.
patent: 4445172 (1984-04-01), Peters et al.
patent: 5095424 (1992-03-01), Woffinden et al.
patent: 5148537 (1992-09-01), Belsan
patent: 5168560 (1992-12-01), Robinson et al.
patent: 5319768 (1994-06-01), Rastegar
patent: 5398325 (1995-03-01), Chang et al.

Affiliated with

Also associated with

Rating

Methods for accessing coincident cache with a bit-sliced archite does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for accessing coincident cache with a bit-sliced archite, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for accessing coincident cache with a bit-sliced archite will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1235191