Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2004-12-22
2008-08-19
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S323000, C713S322000
Reexamination Certificate
active
07415626
ABSTRACT:
Methods for activating operations of a communication device coupled to an external communication bus include detecting a communication event on the external communication bus at a wake up circuit while a host controller coupled to the external communication bus is in an inactive state. An interrupt signal is provided to a processor of the communication device that is operating using a first clock signal running at a first clock rate from a first clock responsive to detection of the communication event by the wake up circuit. A clock enable signal is provided from the processor of the communication device, responsive to the interrupt signal, to a second clock in an inactive state. The second clock is coupled to a second circuit of the communication device separate from the processor of the communications device. Active state operations of the second clock are initiated to generate a second clock signal at a second clock rate greater than the first clock rate responsive to the clock enable signal. Operation of the host controller are initiated responsive to active state operations of the second clock.
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Cotterill Peter
Horton Robert R.
Lilja Patrik
Bae Ji H
Lee Thomas
Myers Bigel & Sibley & Sajovec
Sony Ericsson Mobile Communications AB
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