Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-12-04
2007-12-04
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000
Reexamination Certificate
active
10801893
ABSTRACT:
Dynamic Frequency Scaling (DFS) cache memories that can be accessed during an idle time in a single low frequency DFS clock cycle are disclosed. The access can begin during the idle time in the single low frequency DFS clock cycle and may continue during a subsequent low frequency DFS clock cycle. The idle time can be a time interval in the single low frequency DFS clock cycle between completion of a single high frequency DFS clock cycle and completion of the single low frequency DFS clock cycle. Related circuits and systems are also disclosed.
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Nguyen T
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