Methods, circuits, and systems for refreshing memory cells...

Details Methods, circuits, and systems for refreshing memory cells... Methods, circuits, and systems for refreshing memory cells...

2005-08-16

2005-08-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S230080

Reexamination Certificate

active

06930943

ABSTRACT:
Memory cells in a memory device are refreshed by selecting a first memory cell having a first refresh period to be refreshed. The first memory cell and a second memory cell having a second refresh period together are refreshed responsive to selecting the first memory cell to be refreshed. A circuit for controlling refreshing of memory cells in a memory devices includes an address register that stores the address of a first memory cell having a first refresh period. A comparison circuit compares an input address with the output of the address register and outputs a control signal indicative of a result of the comparison. An address buffer outputs addresses for refreshing the first memory cell and a second memory cell having a second refresh period together responsive to the control signal indicating a match between the input address and the address of the first memory cell.

REFERENCES:
patent: 5867439 (1999-02-01), Asakura et al.
patent: 5999472 (1999-12-01), Sakurai

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