Methods, architectures, circuits, software and systems for...

Details Methods, architectures, circuits, software and systems for... Methods, architectures, circuits, software and systems for...

2008-04-15

2008-04-15

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07360142

ABSTRACT:
Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (i) partitioning the unit of digital data into one or more full data lines and a remainder, wherein each of the full data lines comprises a predetermined number of data blocks, each of the data blocks has a first fixed length, the predetermined number is an integer of at least 2, and the remainder has a length less than the predetermined number times the first fixed length; (ii) if the remainder contains at least one data bit, adding to the remainder a padding vector having a length sufficient to generate a padded data line having the predetermined number of data blocks; and (iii) performing error checking calculations on the full data lines and the padded data line. The present invention reduces the chip area and power consumption, while improving system performance.

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Dror Barash; “Methods, Architectures, Circuits, Software and Systems for Transmission Error Determination”; U.S. Appl. No. 10/690,780, filed Oct. 21, 2003.
Dror Barash; “Methods, Circuits, Architectures, Software and Systems for Determining a Data Transmission Error and/or Checking or Confirming Such Error Determinations”; New U.S. Patent Application, filed Mar. 3, 2004.

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