Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-17
2006-01-17
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06988253
ABSTRACT:
A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins. The operations to recolor the nets preferably include coloring a first pin of a child cell within a parent cell using a pin coloring operation that is a function of a device value of the child cell and a color of each of the pins of the child cell that are independently swappable with the first pin, but is independent of a color of a second pin of the child cell that is dependently swappable with the first pin.
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Johnson, IV Harry Clarkson
Lipton Gary Bruce
White Jonathan Calvin
Myers Bigel & Sibley & Sajovec
Synopsys Inc.
Whitmore Stacy A.
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