Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-04-29
2002-08-13
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S062000, C710S108000, C712S300000
Reexamination Certificate
active
06434635
ABSTRACT:
COPYRIGHT AND TRADEMARK NOTICES
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the U.S. Patent & Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
Intel, Pentium, and i960 are registered trademarks of Intel Corporation. StrongARM is a trademark of Advanced RISC Machines, Ltd. IxWorks is a trademark of Wind River Systems. I
2
O SIG is a trademark of the I
2
O Special Interest Group. Alpha is a trademark of Compaq Computer Corporation. ClearPath is a trademark of Unisys Corporation.
BACKGROUND
1. Field of the Invention
The present invention is directed to computer systems, and more particularly, to methods, apparatus, and computer program products for transferring data between computer system elements in multiple buffers. In general, the present invention addresses situations where the size of the source and destination buffers is fixed, but the source buffer size differs from the destination buffer size.
2. Description of the Prior Art
Data transfers from one memory to another memory in a computer system, particularly where the formats of the two memories differ, sometimes require that a pad (i.e., some pattern of data) be inserted periodically after successive portions of the data are transferred. Other transfers require the removal of this pad as the transfer takes place. Typically, the pad helps to bridge the incompatibilities between memory formats. For example, copending, commonly assigned application Ser. No. 09/144,300, filed Aug. 31, 1998 now abandoned, entitled “Improved Method For Providing Variable Sector-Format Operation To A Computer System” describes a technique in which padding is used to enable a Unisys ClearPath HMP NX enterprise server, which stores data in its internal memory in logical sectors of 180 bytes, to transfer a buffer of data to an attached storage device in which data is arranged in physical sectors of 512 bytes. The Unisys ClearPath HMP NX enterprise server runs under the control of the Unisys MCP operating system and is sometimes also referred to as an MCP server.
FIG. 1
illustrates the padding technique described in the copending application. In the example shown, assume that it is desired to write four logical sectors of data from an application program buffer
10
in an MCP server
12
to an attached storage medium, such as a disk
14
, having a physical sector format that differs in size from the logical sectors in the memory of the MCP server. Specifically, in this example, only two logical sectors will fit within one physical sector, leaving a portion of the physical sector unfilled. According to the method described in the copending application, this mismatch between formats is handled by transferring successive pairs of logical sectors to the storage medium, each followed by a pad of data (152 bytes) that fills out the remainder of the respective physical sectors into which the pairs of logical sectors are stored.
More specifically, the MCP server
12
will make a write request addressed to logical sector
0
of the buffer
10
, with a specified length of four logical sectors. The logical sector request is mapped to the corresponding physical sectors of the disk
14
—in this example, physical sectors
0
and
1
. The input/output subsystem of the MCP server
12
will begin the transfer (step
16
) by writing logical sectors
0
and
1
to physical sector
0
of the disk. The I/O subsystem will then automatically insert a pad of data (the striped area following logical sector
1
) to fill-out the remainder of physical sector
0
(step
18
). Then, logical sectors
2
and
3
will be written to the next physical sector (step
20
), again automatically followed by a pad of data to fill-out the remainder of that physical sector (step
22
).
In general terms, the kind of transfer illustrated in
FIG. 1
can be described as the transfer of a buffer of data of length L from a first memory (e.g., main memory) to a second memory (e.g., disk
14
), wherein a pad of length P is inserted after each successive portion of length S of the data is transferred. In the example of
FIG. 1
, the length S of each successive portion of data transferred is 360 bytes (i.e., two logical sectors) and the length P of the pad is 152 bytes (i.e., the size of the remaining unfilled portion of each physical sector). The need for this kind of transfer exists in numerous other computer systems for a variety of reasons, and the foregoing is just one example.
In Unisys ClearPath HMP NX enterprise servers, the capability to insert a pad after successive portions of a buffer of data are transferred is implemented in hardware.
FIG. 2
is a block diagram illustrating the basic architecture of a ClearPath HMP NX enterprise server. As shown, a main memory
24
is coupled to a memory interface unit (MIU)
30
via a memory bus
28
. The MIU
30
is coupled to several other processors via an internal bus
32
. The other processors include an input/output unit (IOU)
34
, a channel management unit (CMU)
36
, and a data transfer unit (DTU)
38
. The CMU
36
is further connected to an I/O channel adapter
40
. A peripheral unit
42
, such as a disk drive or other secondary storage medium, connects to the I/O channel adapter
40
. It should be noted that in addition to IOU
34
, which is an input/output unit, the entire module, including the MfU
30
, the IOU
34
, the CMU
36
, and the DTU
38
is referred to as an input/output module (IOM).
The MIU
30
provides the interface between the above mentioned processors and units and the main memory
24
. The MIU
30
handles the buffering and issuing of addresses to main memory
24
for store and fetch operations. The MWU
30
also handles translation between logical and physical addresses and arbitration of a plurality of requests from the memory
24
.
The CMU
36
manages data movement between the main memory
24
and any peripheral I/O units (e.g., disks and tape drives) which may be coupled to the processing system. The CMU
36
communicates with external channels, such as the channel adapter
40
, through a channel service bus (not shown). The DTU
38
controls block data transfer from one location in main memory
24
to another upon the request of the IOU
34
. The DTU
38
is also used for disk caching.
The IOU
34
performs high level I/O functions, such as the scheduling of I/O jobs, the selection of data paths over which I/O jobs are performed, the gathering of job statistics, and the management of I/O devices and of a disk cache. The IOU
34
determines whether padding is required during transfer of a buffer of data from main memory to a peripheral unit
42
, such as a disk drive. For example, the IOU
34
detects when a disk unit having a 512 byte physical sector format is attached to the channel adapter
40
and programs subsequent data transfers to the disk unit so that the padding method illustrated in
FIG. 1
is employed. The actual padding operation is carried out by proprietary hardware on the channel adapter
40
. Specifically, the hardware on the adapter is programmable to insert P bytes of data after every S bytes of data is transferred from the main memory
24
to the peripheral unit
42
.
Today, there is an ever increasing push for companies in the computer industry to supply systems that are built using industry standard components, relying less on proprietary designs. One area in which this trend is strong is input/output processing. There have been a number of industry-wide initiatives to develop standard specifications for the design and operation of input/output devices and subsystems. For example, the computer industry has recently begun to adopt and to implement solutions based on the Intelligent I/O (I
2
O) Architecture Specification, which describes standard specifications for the development of intelligent I/O adapters and associated device driver sof
Case Timothy
Coffman Richard
Atlass Michael B.
Elam Abdelmomem
Gaffin Jeffrey
Rode Lise A.
Starr Mark T.
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