Methods and systems to write to soft error upset tolerant...

Details Methods and systems to write to soft error upset tolerant... Methods and systems to write to soft error upset tolerant...

2008-09-29

2010-10-05

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular write circuit

C365S189050, C365S190000

Reexamination Certificate

active

07808845

ABSTRACT:
Methods and systems to write to redundant storage latches, or storage cells, including soft error upset tolerant latches and feedback-interlocked redundant storage cells, including to write a logic value to one of a plurality of same sense storage nodes, and to write a complementary logic value to a selected one of a plurality of opposite sense storage nodes responsive to the logic value. Remaining storage nodes may be written to through circuitry within the storage cell. Logic values may be output substantially simultaneously with corresponding write operations. A system may include a multiple logic level write circuit to write to the first same sense storage node, and first and second single logic level write circuits to write to the first and second opposite sense storage nodes, respectively.

REFERENCES:
patent: 6696873 (2004-02-01), Hazucha et al.
patent: 6826090 (2004-11-01), Chu et al.
patent: 7023235 (2006-04-01), Hoff
patent: 7038515 (2006-05-01), Rusu et al.
patent: 7161404 (2007-01-01), Hazucha et al.
patent: 7576583 (2009-08-01), Kuboyama et al.
patent: 2004/0130351 (2004-07-01), Hazucha et al.
Calin, T. et al., “Upset Hardened Memory Design for Submicron CMOS Technology”,IEEE Transactions on Nuclear Science, vol. 43, No. 6, (Dec. 1996),2874-2878.
Hazucha, Peter et al., “IEEE Journal of Solid-State Circuits, vol. 39, No. 9,”, (Sep. 2004),1536-1543.
Krueger, Dan et al., “Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium Processor”,2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Session 4, Microprocessors 4.7, (Feb. 4, 2008),2 pages.

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