Methods and systems for Viterbi decoding

Details Methods and systems for Viterbi decoding Methods and systems for Viterbi decoding

2007-10-23

2007-10-23

Nguyen, Phu K. (Department: 2628)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000, C709S213000

Reexamination Certificate

active

10948545

ABSTRACT:
An execution unit and method for performing Viterbi decoding is provided. The instruction may be built into an execution unit which executes other instructions, or in its own execution unit. In an example implementation, the instruction is used in implementing the central-office modem (ATU-C) of an asymmetric digital subscriber line (“ADSL”) system. In the example implementation, the new instruction takes as input eight input metrics and eight state metrics, and returns as output eight updated state metrics and eight decision bytes. The decision bytes contain: two ‘path’ bits to enable the previous state to be quickly identified; bits to enable the input bits to be quickly identified; and a carry bit to allow the full value of a state metric to be reconstructed, even though during the calculation only the bottom bits are calculated.

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