Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-05-29
2007-05-29
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C326S026000, C333S032000, C333S033000, C333S124000
Reexamination Certificate
active
10991724
ABSTRACT:
A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The inductance is configured to reduce signal mismatch between complementary signals of the differential output signal. The signal mismatch is a result of having each of the complementary signals exposed to different capacitive loading. A device and system is also provided, which include integrating an inductor between the output leads of a differential driver. The inductor is sized for the particular frequency of operation, and the inductor provides an inductance that assists in eliminating mismatch between the complementary signals of the differential output. A reduction and/or elimination of the mismatch will assist in improving the rise-time of the differential signals.
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Hargrove Michael
Meltzer David
Chang Daniel D.
Seiko Epson Corporation
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