Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-03-07
2006-03-07
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C711S105000, C711S150000, C711S151000, C711S154000, C711S167000, C711S168000
Reexamination Certificate
active
07010654
ABSTRACT:
Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.
REFERENCES:
patent: 6622225 (2003-09-01), Kessler et al.
patent: 2004/0059880 (2004-03-01), Bennett
patent: 2005/0097265 (2005-05-01), Shrader et al.
Blackmon Herman L.
Kirscht Joseph A.
Marcella James A.
Vanderpool Brian T.
International Business Machines - Corporation
Namazi Mehdi
Padmanabhan Mano
Patterson & Sheridan LLP
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