Methods and systems for providing variable clock rates and...

Details Methods and systems for providing variable clock rates and... Methods and systems for providing variable clock rates and...

2011-07-19

2011-07-19

Tse, Young T. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C713S400000, C713S503000, C713S600000

Reexamination Certificate

active

07983374

ABSTRACT:
A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.

REFERENCES:
patent: 4330862 (1982-05-01), Smolik
patent: 6509851 (2003-01-01), Clark et al.
patent: 2004/0218634 (2004-11-01), Peng et al.
patent: 2005/0180536 (2005-08-01), Payne et al.
IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements, Part 3: Carrier sense multiple access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Computer Society, IEEE Std. 8023™, Dec. 26, 2008, 671 pages.

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