Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-05-15
2007-05-15
Beausoliel, Robert W (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C714S055000, C714S051000, C711S106000
Reexamination Certificate
active
10435077
ABSTRACT:
Methods and systems for preserving dynamic random access memory content in response to a hung processor condition are disclosed. In order to preserve dynamic random access memory content, a first watchdog timer is initiated and strobed at a predetermined time interval less than its timeout value. If a hung processor condition occurs and the strobing of the first watchdog timer fails, the first watchdog timer generates a non-maskable interrupt to the processor. The non-maskable interrupt triggers the processor to execute an interrupt service routine. If the processor is able to execute the interrupt service routine, the interrupt service routine controls the processor to perform a selective system reset and preserve dynamic random access memory contents. If the processor is not capable of executing the interrupt service routine, a board reset occurs and dynamic random access memory contents are cleared.
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Newton, Harry, Newton's Telecom Dictionary, Feb. 2002, 18th Ed., pp. 668-669.
Baus Jeremy T.
Pail Michael R.
Wallace Robert
Beausoliel Robert W
Jenkins Wilson Taylor & Hunt, P.A.
McCarthy Christopher
Tekelec
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