Methods and systems for predicting IC chip yield

Details Methods and systems for predicting IC chip yield Methods and systems for predicting IC chip yield

2002-10-24

2004-06-15

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S109000, C702S182000

Reexamination Certificate

active

06751519

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to methods and apparatus for detecting defect densities in a semiconductor integrated circuit product and/or test structure to thereby predict product-limited yields and the product lot yields. More particularly, it relates to mechanisms for prediction of the end-of-line product wafer test yield from the in-line testing and/or inspection database at high confidence levels.
Conventionally, the test structures on a test wafer or product wafer are inspected or tested for defects, more specifically for electrical fails. The resulting defect sample may then be used to predict the product-chip yield in a product wafer lot. The test structures may be inspected using either optical inspection or scanning electron microscope tools. In an optical inspection, a beam of light is directed towards the test structures and the scattered light is then analyzed to determine whether defects are present within the test structures.
Another type of inspection is referred to as a voltage contrast inspection, using a scanning electron microscope. The voltage contrast technique operates on the basis that potential differences in the various conductive shapes of a sample under examination cause differences in, typically, the secondary and/or backscattered electron emission intensities when the sample is the target of a low-energy and high-current electron beam. The potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
An electron detector is used to measure the intensity of the secondary and/or backscattered electron emission that originates from the path swept by the scanning electron beam. Images may then be generated from these electron emissions. A defective portion can be identified from the unintended potential state or appearance of the portion under inspection. The test structure portion under inspection is typically designed to produce a particular potential and resulting brightness level in an image during the voltage contrast inspection. Hence, when the scanned portion's potential and resulting image appearance differs significantly from the expected result, the scanned portion is classified as a defect.
Several inventive test structures designed by the present assignee are disclosed in U.S. Pat. No. 6,433,561 by Akella V.S. Satya et al., issued Aug. 13, 2002, which patent is incorporated herein by reference in its entirety. One test structure is designed to have alternating high and low potential conductive lines during a voltage contrast inspection. In one inspection application, the low potential lines are at ground potential, while the high potential lines are at a floating potential. However, if a line that is meant to remain floating shorts to an adjacent grounded line, both lines will then be at a low potential during a voltage contrast inspection. If there is an open defect present within a line that is designed to be coupled to ground, this open will cause a portion of the line to be left at a floating potential to thereby produce a high potential during the voltage contrast inspection. Both open and short defects cause two adjacent lines to have the same potential during the voltage inspection.
The results from inspecting the test structures, typically in a test chip, may then be used to predict product wafer-test yield of a product chip that is fabricated with the same process as the test chip. Such product wafer test yield is generally a product of the product-limited yields for all the primary defect mechanisms predicted from the corresponding test-structure yields. Unfortunately, product wafer test yield is typically only predicted after all processes, which contribute to all of the primary defect mechanisms, are performed. For example, the processes for each of the conductive interconnect layers and their individual test structures are completed so that the test structure yields from each interconnect layer may be obtained from each interconnect layer. The resulting test structure yields may then be combined appropriately to predict the product chip yield. Thus, predicted product wafer test yield excursions cannot be identified until a significant number of the processes are complete. The excursion may result in a significant loss of product at considerable expense. Additionally, since excursions are predicted rather late in the fabrication flow, one misses an opportunity to dynamically correct process errors early during the fabrication process.
Accordingly, there is a need for improved techniques for managing yield of integrated circuit (IC) wafers or modules. Additionally, there is a need to identify yield excursions early in the fabrication process.
SUMMARY OF THE INVENTION
Accordingly, techniques and systems for efficiently managing yield are provided. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information (e.g. components) includes a systematic yield (Y
o
), a defect density (DD), and a defect clustering factor (&agr;) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer test yield may be predicted at any stage in the fabrication process based on the average yield information maintained for previously fabricated wafer lots.
In one embodiment, a method of managing and predicting product yield for a plurality of semiconductor products is disclosed. In one implementation, the semiconductor product is a product wafer lot and the predicted product yield is a predicted product wafer test yield. After a first process is performed on the semiconductor product, one or more test structures for the first process are inspected to obtain yield information related to a test structure yield for the first process. In one example, the yield information includes systematic yield, a defect density, and possibly a defect cluster factor &agr;. A product yield of the semiconductor product at a time of fabrication completion is then predicted. The prediction is dynamically based on the obtained yield information for the first (e.g., current) process and an average of yield information for any remaining process(es) for the semiconductor product obtained from previously fabricated semiconductor products.
In a further aspect, the method includes (a) determining whether an excursion has occurred based on the predicted product yield; (b) when it is determined that an excursion has occurred, executing an excursion plan; and (c) when it is determined that an excursion has not occurred, performing a next process on the semiconductor product. In yet a further implementation, the method includes (d) after the next process is performed on the semiconductor product, inspecting one or more test structures for the next process to obtain yield information related to a test structure yield for the next process; and (e) predicting the product yield of the semiconductor product at a time of fabrication completion for the semiconductor product. The prediction is dynamically based on the obtained yield information for the first and next process for the semiconductor product and an average of yield information for any remaining process(es) for the semiconductor product from previously fabricated semiconductor products.
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