Methods and systems for optimizing designs of integrated...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

07873930

ABSTRACT:
Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within the first set have been used for routing and routing, using a second set of wiring resources in the representation, connections on the IC without checking whether wiring resources within the second set have been previously used to route connections, wherein wiring resources in the second set differ, on average, in physical size, from wiring resources in the first set. Other methods and systems for optimizing and/or designing ICs are also described, and machine-readable media containing executable program instructions which cause systems to perform one or more of these methods are also described.

REFERENCES:
patent: 6438735 (2002-08-01), McElvain et al.
patent: 6449762 (2002-09-01), McElvain
patent: 6973632 (2005-12-01), Brahme et al.
patent: 7131096 (2006-10-01), Balsdon et al.
patent: 7149997 (2006-12-01), Young et al.
patent: 7519927 (2009-04-01), Hryckowian et al.
patent: 2002/0083407 (2002-06-01), Suzuki et al.
PCT Search Report and Written Opinion for PCT/US2007/007311, mailed Sep. 14, 2007, 11 pages.
Rautela D et al., “Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources”, VLSI, 2005, Proceedings. IEEE Computer Society Annual Symposium on Tampa, FL, USA May 11-12, 2005, Piscataway, NJ, USA, IEEE, May 11, 2005. pp. 232-237.
Murooka T et al., “An architecture-oriented routing method for FPGAs having rich hierarchical routing resources”, Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific Yokohama, Japan Feb. 10-13, 1998, New York, NY, USA IEEE, US, Feb. 10, 1998, pp. 527-533.
Zhibin Dai et al., “Routability Prediction for field programmable gate arrays with a routing hierarchy”, VLSI Design, 2003. Proceedings. 16th International Conference on Jan. 4-8, 2003, Piscataway, NJ, USA, IEEE, Jan. 4, 2003, pp. 85-90.
M. Hrkic, J. Lillis, G. Beraudo, “An Approach to Placement-Coupled Logic Replication”, Proceedings of the 41stAnnual Conference on Design Automation, pp. 711-716, Jun. 7-11, 2004.
PCT Notification Concerning Transmittal of International Preliminary Report on Patentability (Chapter of the Patent Cooperation Treaty);and Written Opinion for PCT/US2007/007311, International filing date Mar. 23, 2007, mailed Oct. 9, 2008, 7 (two-sided) pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods and systems for optimizing designs of integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and systems for optimizing designs of integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and systems for optimizing designs of integrated... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2733561

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.