Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-01
2008-08-05
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07409658
ABSTRACT:
Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections between clusters. Clustering optionally includes multi-level clustering. The clusters, and any unclustered objects, are floorplanned. Floorplanning positions the clusters so as to reduce or minimize the length of interconnections between the clusters. Objects within the clusters are then placed within the area assigned to the corresponding clusters. Placement optionally utilizes placement-based wire load models to accurately predict timing issues. A bottoms-up procedure is optionally performed during clustering and/or floorplanning, whereby area and/or size constraints of clustered objects are taken into account.
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Chiang Jack
Magma Design Automation Inc.
Parihar Suchin
Sterne Kessler Goldstein & Fox P.L.L.C.
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