Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-09-29
2010-10-05
Patel, Hetul (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S114000, C711S161000, C711S162000, C707S640000
Reexamination Certificate
active
07809912
ABSTRACT:
Methods and systems are provided for minimizing disruptions when host data on a source logical unit is migrated onto a target logical unit. I/O requests are managed in a particular order during various states of the migration. After the target logical unit is synchronized with the source logical unit and before a commitment to the target logical unit is made, the target logical unit can be evaluated. At that point, the migration can be aborted. During the evaluation of the target logical unit, I/O requests that were directed to the source logical unit are redirected to the target logical unit and I/O requests that were directed to the target logical unit are redirected to the source logical unit. The disclosed methods and systems are equally effective at enabling less disruptive virtualization of a source logical unit as a target logical unit.
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Bappe Michael E.
Gill Todd R.
Raizen Helen S.
Daly, Crowley & Mofford & Durkee, LLP
EMC Corporation
Patel Hetul
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