Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-05-08
2007-05-08
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
10409569
ABSTRACT:
Methods and systems for improving delayed read handling in a loop of delayed commands among a larger set of commands in a queue of commands are disclosed. In general, when commands in a delayed loop are completed out of order, “holes” are left in the command queue. Skipping over such “holes” consumes multiple clock cycles before another command can be issued, as each “hole” must be examined first in order to determine that it no longer contains a valid read command. A loop of delayed read commands can thus be created from among a larger set of commands in a queue of commands with each command entry having a pointer to the next valid command. Valid delayed read commands in the loop of commands can then be processed by automatically advancing between any two valid delayed read commands among the loop of commands. In this manner, the time to advance between any two commands in the delayed read loop is constant and PCI read performance thereof can be dramatically improved.
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Solomon Richard L.
Thomas Jill A.
LSI Logic Corporation
Ortiz & Lopez PLLC
Patel Nimesh
Perveen Rehana
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