Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2008-12-31
2011-11-29
Hafiz, Tariq (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S002000, C710S008000, C710S033000
Reexamination Certificate
active
08069285
ABSTRACT:
Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an error sensed on the link. Based on the at least one counter, the SAS/SATA device determines whether to maintain the first signal rate. The link is re-established at a second signal rate based on the determination such that the second signal rate is lower than the first signal rate.
REFERENCES:
patent: 2004/0199834 (2004-10-01), Fukae
patent: 2006/0041614 (2006-02-01), Oe
Lanzani, Christian, OBSAI RP3-01 6.144 Gbps Interface Implementation, 2007, FPGAworld.com, [online, accessed on Jul. 27, 2011], URL: http://www.obsai.org.
Einsweiler Brian K.
Faulhaber Steven F.
McGinley Jason C.
McKay Luke E.
Volz Warren R.
Duft Bornsen & Fishman LLP
Hafiz Tariq
LSI Corporation
Sun Scott
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