Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2004-06-30
2009-06-23
Patel, Niketa I (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C711S163000
Reexamination Certificate
active
07552317
ABSTRACT:
Methods, systems, and articles of manufacture consistent with the present invention provide a memory instruction manager for managing the execution of instructions associated with a program. The memory instruction manager assigns a first group identifier to a first instruction associated with a program and to a second instruction associated with the program, and provides, after the first instruction, a memory barrier instruction having the first group identifier such that one or more processors with access to the program are inhibited from executing the second memory instruction until the first memory instruction is executed.
REFERENCES:
patent: 6651151 (2003-11-01), Palanca et al.
SPARC International, Inc., “The SPARC Architecture Manual”, Version 9, PTR Prentice Hall, No. SAV09R1459912, pp. i-xi, 182-188, 2000.
Moll Jesse R
Patel Niketa I
Sonnenschein Nath & Rosenthal LLP
Sun Microsystems Inc.
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