Methods and systems for generating latch clock used in...

Details Methods and systems for generating latch clock used in... Methods and systems for generating latch clock used in...

2006-11-28

2006-11-28

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189070, C365S191000

Reexamination Certificate

active

07142470

ABSTRACT:
Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.

REFERENCES:
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6137734 (2000-10-01), Schoner et al.
patent: 6930524 (2005-08-01), Drexler

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