Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Patent
1997-10-15
2000-02-29
Peikari, B. James
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
711219, G06F 932
Patent
active
06032242&
ABSTRACT:
Methods and systems for generating alternate and zigzag address scans in a reconfigured two-dimensional map under the MPEG-1 and MPEG-2 are provided. In one embodiment, a control signal generator determines the subsequent alternate address based on the present alternate address. In another embodiment, the control signal generator determines the subsequent zigzag address based on the present zigzag address. The subsequent address is generated by incrementing, decrementing, or resetting a pair of up/down counters that are coupled to the inputs of the control signal generator.
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Industrial Technology Research Institute
Peikari B. James
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