Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-01-27
2001-02-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06192504
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to the design development of computer hardware and the simulation of electrical and logical behavior of digital hardware such as electronic circuits. In particular, the invention provides a method and an apparatus allowing to convert a functional description of digital hardware into a complete netlist.
BACKGROUND OF THE INVENTION
Traditional approaches for the design specification of computer hardware are based on either a netlist register transfer level (RTL) description or a functional hardware description. A functional description does not represent the detailed hardware layout with all interconnections and functional elements, but it is predominantly used to quickly provide a hardware specification which can be executed and examined or verified at the earliest development stage. Hereby the functional properties envisaged for the hardware are converted to functional features which are then linked together.
A functional specification can be set up in any programming language like ‘C’ or ‘C++’, but often specifically modified languages like ‘BEHAVIOUR’ are utilized to take particular hardware properties into account. After having been compiled for the target computer system, the functional specification can be used for the hardware simulation on a standard computer using an operating system like ‘UNIX’ (operating system developed at Bell laboratories, registered trademark of UNIX system laboratories). The functional description approach therefore allows to present complex hardware structures in a manner that enables to detect hardware failures as early as possible in the design phase.
In contrast to the above functional approach, a netlist description, in any case, is necessary to get a hardware product for the design. The netlists can be described by particular hardware description languages like ‘DSL’ (Hardware Design Language, developed at IBM development laboratory, Boeblingen, Germany) which is characterized by utilizing only one data structure namely bundles of conductors. Therefore, ‘DSL’ requires only attribute declarations for Input/Output features or clock signals. Storage elements like registers and arrays are regarded as blocks. The vocabulary of that language embraces only operators with a low hardware complexity like logic operators ‘compare’, ‘if-then’, ‘add’, and ‘subtract’.
An other netlist description approach is ‘VHDL’, a programming language like ‘ADA’, which is extended by particular hardware operations. Accordingly, that language comprises a number of data structures and all statements of a common programming language like ‘loop’ statements. By the provision of particular statements for timing and signalling, ‘VHDL’ becomes a real hardware description language. One disadvantage of ‘VHDL’ is that simulation is event driven due to the required signal definitions.
The prementioned description languages are rather different from the predescribed functional approach with regard to the respective underlying methodology. A simulation procedure based on the functional approach executes the complete hardware sequentially function by function. However, for each state transition, not all functions have to be executed since most of them exclude each other.
In contrast to that, in the netlist approach, the hardware is described in parallel whereby functional relationships become not evident. Therefore, in order to simulate a netlist, the netlist description has to be analyzed, sorted, and stored as a design model in a particular data structure. Thereafter a simulator engine can execute that design model. But the functional properties of the simulated hardware are entirely lost. Therefore that approach is rather time consuming. But at this time, no method exists which enables a simple or even automatic conversion from a functional description of hardware to a correct and complete netlist. Therefore, for all designs, expensive netlist specifications have to be generated and verified manually.
Further, the design of today's complex digital signal processing systems increasingly relies on sophisticated design tools for a functional analysis and simulation. Recent work has been concerned with the integration of such simulation tools, wherein data flow-oriented approaches have proven to be very well suited for both tasks due to the nature of most digital signal processing applications. Further known is the integration of control flow into data flow oriented simulation and syntheses.
Various state-machine development tools for high-level design entry and simulation are known in the art in order to shorten the design time and to ensure the correctness of the simulation results. For the analysis of a typical computer design, the sequential control logic of the hardware system realized as finite state machines is one of the major design efforts.
An other major problem which is addressed e.g. in an article by A. Aziz et al. published in IEEE Computer Society Press, Los Alamitos, USA, and entitled “Minimizing Interacting Finite State Machines: A Compositional Approach to Language Containment”, is compositional minimization of collections of interacting finite state machines that arise in the context of formal verification of hardware designs. It is recognized by the authors that much of the behavior of a designed system is redundant with respect to a given property being verified, and so the system can be replaced by substantially simpler representations. The authors show that these redundancies can be captured by computing states that are input-output equivalent in the presence of fairness. Since computing complete equivalences is computationally expensive, they further propose a spectrum of approximations which are efficiently computable. For instance, procedures are described that hierarchically minimize the system with respect to explicit representations.
Thereupon, a number of approaches in the field of translation of data flow information into a hardware description language are known. In an article by W. H. Chou and S. Y. Kung published in IEEE Computer Society Press, Los Alamitos, USA, and entitled “Register Transfer Modelling and Simulation for Array Processors”, a register transfer modelling scheme is described where a data flow graph of the design is translated into a register transfer language which is further combined with a hardware description module. Hereby an interactive simulator is implemented to simulate the behavior of such a system.
Further, in an article by A. D. Gordon, published in IEEE Computer Society Press, Los Alamitos, USA, and entitled “The Formal Definition of a Synchronous Hardware-Description”, a hardware verification method is described which provides connections between a language used in practice to design a circuit and an other language which is used for research into hardware verification. Hereby a simple data flow language is used for specifying digital signal processing circuits wherein a higher-order logic is extensively used for research into hardware verification. Particular, a combination of operational and predictive semantics is used to define formally a substantial subset of the data flow language by mapping that language definitions into the high-order logic predicates.
An other high-level hardware design environment is disclosed in an article by F. Rocheteau and N. Halbwachs published in Elsevier, Amsterdam, Netherlands, in 1992 and entitled “POLLUX: LUSTRE BASED HARDWARE DESIGNED ENVIRONMENT”. Hereby a design description is written in a data-flow language, and used by a different tool to produce the corresponding synchronous circuit or a simulation program that can be compiled and executed on a sequential machine.
Beyond the above approaches, also object-oriented concepts for hardware description languages are already known, for instance, from an article by A. J. Van der Hoeven et al. published in IEEE Computer Society Press, Los Alamitos, USA, and entitled “A Hardware Designed System Based on Object-Oriented Principles”. Most hardware description languages
Pfluger Thomas
Schubert Klaus-Dieter
International Business Machines - Corporation
Otterstedt Paul J.
Siek Vuthe
Smith Matthew
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