Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-04-11
2003-08-12
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185240, C365S185280
Reexamination Certificate
active
06606273
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor device fabrication and more particularly to testing tunnel oxide reliability in flash memory devices.
BACKGROUND OF THE INVENTION
Nonvolatile memory is becoming popular in modern electronic devices where data retention is needed when the devices are powered down. Nonvolatile memories include electrically programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROMs), wherein a large number of memory cells are constructed having an electrically isolated gate, referred to as a floating gate. A control gate is formed above the floating gate and isolated therefrom for operating the cell in program, erase, verify, and read operations. Data is stored in the memory cells in the form of charge on the floating gates. Electrical charge is provided to or removed from the floating gates by program and erase operations, respectively.
Another type of non-volatile memory is flash memory which is a derivative of EPROM and EEPROM. Unlike EPROM and EEPROM devices, certain types of flash memory can be reconfigured by erasure or reprogramming inside a system, without requiring special voltages for such reconfiguration. Flash memory devices are also generally lower in cost and available in higher densities than EEPROM. As a result, flash memory is becoming popular in a number of applications such as personal computers and peripherals, telecommunication switches, cellular phones, and internetworking, instrumentation and automotive devices, and emerging consumer-oriented voice, image and data storage products such as digital cameras, digital voice recorders, personal digital assistants (PDAs), and the like.
Such flash memory are commonly erased and reprogrammed in multiple-cell groups referred to as blocks. In modern floating gate flash memory cells, a program operation generates channel hot electrons (CHE) which are transported into the floating gate, causing an increase in the threshold voltage of the cell, which can subsequently be detected by reading the cell. A flash memory cell is typically programmed by applying a relatively high voltage to a control gate, grounding the source, and applying a predetermined voltage to the drain, where the drain potential is higher than that of the source. This generates vertical and lateral electric fields along the length of the channel from the source to the drain. These fields in turn cause electrons to be drawn off the source, which accelerate toward the drain, gaining energy along the way.
Electrons which achieve a certain energy level are able to jump over the potential barrier of the tunnel oxide and into the floating gate. These electrons become trapped in the floating gate which is surrounded by insulators (e.g., an interpoly dielectric between the floating gate and the control gate, and the underlying tunnel oxide). This trapping of electrons in the floating gate causes an increase in the threshold voltage of the cell, thereby programming the cell. The increase in the cell threshold voltage can then be detected during a read operation to ascertain the data stored in the cell.
In a read operation, a predetermined gate voltage is applied to the control gate, which is greater than the threshold voltage of an unprogrammed or erased cell, but less than the threshold voltage of a programmed cell, while a voltage is applied between the source and the drain. The current through the channel is measured and compared with a reference current to determine whether the cell has been programmed or not. If the measured current is above the reference value, then the cell has not been programmed (e.g., representing a first logic state such as a binary “0”). Alternatively, if the cell current is below the reference amount, then the cell has been programmed (e.g., thus representing a second logic state, such as a binary “1”).
Flash cell erasure typically involves a Fowler-Nordheim tunneling effect, wherein electrons pierce through the tunnel oxide material between the floating gate and an underlying channel. In this way electronic charge is removed from the floating gate of a memory cell, thereby restoring the cell threshold voltage to the original (e.g., “unprogrammed” value). Various techniques are possible for erasing flash memory cells. One flash erasure technique involves applying a relatively high positive voltage to the source while the control gate is held at ground potential or connected to a negative voltage, and the drain is allowed to float. This generates a strong electric field across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate undergo Fowler-Nordheim tunneling through the tunnel oxide to the source. In a channel-erase technique, a positive voltage is applied to the substrate beneath the channel, such as a P-well, and a relatively large negative voltage is applied to the control gate while the source and drain are allowed to float. This causes a large field between the gate and the substrate, resulting in Fowler-Nordheim tunneling of electrons from the floating gate through the tunnel oxide and into the channel.
Both the channel hot electron effect during flash memory programming operations along with the Fowler-Nordheim tunneling effect during erase operations cause degradation of the charge retention reliability of flash memory devices. The transfer of electrons into and out of the floating gate stresses the tunnel oxide material between the floating gate and the underlying channel. In the manufacture of flash memory devices, it is desirable to characterize the quality of the tunnel oxide to ensure that finished flash memory devices will operate properly for a certain number of data programming and erasure operations.
Toward that end, testing of samples is commonly done, in which sample memory devices are taken from lots of packaged memory devices and subjected to testing operations to ascertain the reliability of the tunnel oxide material therein. To illustrate such testing,
FIG. 1
shows a conventional flash memory testing procedure
2
, wherein samples are subjected to 100,000 program and erase cycles at an elevated temperature. A semiconductor wafer is processed at
4
to form flash memory devices therein, wherein many such devices are fabricated in individual die sections of the wafer according to known flash memory manufacturing techniques. Following processing of the flash memory wafer at
4
, individual device dies are separated or singulated at
6
and packaged at
8
. Thereafter at
10
, a test device is selected from the packaged memories and a threshold voltage or voltages associated with the one or more memory cells in the test device is measured at
12
prior to program/erase operation cycling.
At
14
, the temperature of the test device is elevated to 90 degrees C. and a program test operation is performed. The program operation at
14
involves programming one or more cells corresponding to the initial threshold voltage measurement at
12
, using programming conditions similar to those encountered in normal operation of the device. Thereafter, the programmed cell or cells are erased at
16
, again using erase conditions similar to normal erase operations at an elevated temperature of 90 degrees C. A counter is checked at
18
to ascertain whether 100,000 program/erase cycles have been performed. If not (NO at
18
), the count is incremented at
20
, and the programming and erasure of the target cell(s) is repeated at
14
and
16
. The process continues in this fashion until the target cell in the test device has been programmed and erased 100,000 times (YES at
18
), at which time the device is baked at
22
.
Following the simulation of 100,000 program and erase cycles at
14
-
20
above, the final threshold voltage of the test device is measured at
24
, and a threshold voltage shift is calculated at
26
by computing the difference between the measured initial (e.g., pre-stress) and final (e.g., post-stress) threshold voltages from steps
12
and
24
,
Guo Xin
Wang Zhigang
Yang Nian
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Le Thong Q.
LandOfFree
Methods and systems for flash memory tunnel oxide... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and systems for flash memory tunnel oxide..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and systems for flash memory tunnel oxide... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3121855