Methods and systems for first occurence debugging

Details Methods and systems for first occurence debugging Methods and systems for first occurence debugging

2007-02-20

2010-10-26

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S015000, C714S045000

Reexamination Certificate

active

07823022

ABSTRACT:
An embodiment relates generally to an apparatus for debugging. The apparatus includes a memory configured to store data and an arithmetic logic unit configured to perform logical and arithmetic operations. The apparatus also includes a control unit configured to interface with the memory and arithmetic logic unit and to decode instructions. The control unit is configured to write a data state designated to be overwritten by a currently executing instruction to a buffer allocated in the memory in response to a trace debug flag being set.

REFERENCES:
patent: 5933626 (1999-08-01), Mahalingaiah et al.
patent: 5944841 (1999-08-01), Christie
patent: 6154856 (2000-11-01), Madduri et al.
patent: 6240529 (2001-05-01), Kato
patent: 7343588 (2008-03-01), Bates et al.
patent: 2003/0233601 (2003-12-01), Vaid et al.
patent: 2007/0006047 (2007-01-01), Zhou et al.
patent: 2008/0127098 (2008-05-01), Bates et al.

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