Methods and systems for failure isolation and data recovery...

Details Methods and systems for failure isolation and data recovery... Methods and systems for failure isolation and data recovery...

2007-11-16

2010-11-16

Baderman, Scott T (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S042000, C714S047300, C714S048000

Reexamination Certificate

active

07836340

ABSTRACT:
A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device. Also, a method of recovering data from a configuration of series-connected semiconductor memory devices having undergone a failure, comprising: placing an operable device of the configuration into a recovery mode of operation; while the operable device is in the recovery mode of operation, retrieving data currently stored by the operable device; and storing the retrieved data in an alternate memory facility.

REFERENCES:
patent: 4174536 (1979-11-01), Misunas et al.
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5319598 (1994-06-01), Aralis et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5452259 (1995-09-01), McLaury
patent: 5475854 (1995-12-01), Thomsen et al.
patent: 5636342 (1997-06-01), Jeffries
patent: 5721840 (1998-02-01), Soga
patent: 5729683 (1998-03-01), Le et al.
patent: 5740379 (1998-04-01), Hartwig
patent: 5768173 (1998-06-01), Seo et al.
patent: 5777488 (1998-07-01), Dryer et al.
patent: 5806070 (1998-09-01), Norman et al.
patent: 5828899 (1998-10-01), Richard et al.
patent: 5835935 (1998-11-01), Estakhri et al.
patent: 5859809 (1999-01-01), Kim
patent: 5896400 (1999-04-01), Roohparvar et al.
patent: 5898615 (1999-04-01), Chida
patent: 6002638 (1999-12-01), John
patent: 6009479 (1999-12-01), Jeffries
patent: 6052331 (2000-04-01), Araki et al.
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6148363 (2000-11-01), Lofgren et al.
patent: 6304921 (2001-10-01), Rooke
patent: 6317350 (2001-11-01), Pereira et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6317812 (2001-11-01), Lofgren et al.
patent: 6453365 (2002-09-01), Habot
patent: 6658509 (2003-12-01), Bonella et al.
patent: 6680904 (2004-01-01), Kaplan et al.
patent: 6715044 (2004-03-01), Lofgren et al.
patent: 6763426 (2004-07-01), James et al.
patent: 6792003 (2004-09-01), Potluri et al.
patent: 6799133 (2004-09-01), McIntosh et al.
patent: 6928501 (2005-08-01), Andreas et al.
patent: 6931571 (2005-08-01), Bernadat et al.
patent: 6944697 (2005-09-01), Andreas
patent: 6950325 (2005-09-01), Chen
patent: 6961882 (2005-11-01), Manfred et al.
patent: 6978402 (2005-12-01), Hirabayashi
patent: 6996644 (2006-02-01), Schoch et al.
patent: 7024605 (2006-04-01), Sera et al.
patent: 7031221 (2006-04-01), Mooney et al.
patent: 7032039 (2006-04-01), DeCaro
patent: 7047450 (2006-05-01), Iwamitsu et al.
patent: 7072994 (2006-07-01), Britton
patent: 7093076 (2006-08-01), Kyung
patent: 7130958 (2006-10-01), Chou et al.
patent: 7168027 (2007-01-01), Lee et al.
patent: 7210634 (2007-05-01), Sapiro
patent: 7308524 (2007-12-01), Grundy et al.
patent: 2002/0188781 (2002-12-01), Schoch et al.
patent: 2004/0001380 (2004-01-01), Becca et al.
patent: 2004/0019736 (2004-01-01), Kim et al.
patent: 2004/0024960 (2004-02-01), King et al.
patent: 2004/0039854 (2004-02-01), Estakhri et al.
patent: 2004/0073829 (2004-04-01), Olarig
patent: 2004/0199721 (2004-10-01), Chen
patent: 2004/0230738 (2004-11-01), Lim et al.
patent: 2005/0160218 (2005-07-01), See et al.
patent: 2005/0213421 (2005-09-01), Polizzi et al.
patent: 2005/0262422 (2005-11-01), Yamauchi
patent: 2006/0005078 (2006-01-01), Guo et al.
patent: 2006/0050594 (2006-03-01), Park
patent: 2006/0239107 (2006-10-01), Boecker et al.
patent: 2007/0043975 (2007-02-01), Varadarajan et al.
patent: 2007/0076479 (2007-04-01), Kim et al.
patent: 2007/0076502 (2007-04-01), Pyeon et al.
patent: 2007/0096774 (2007-05-01), Yang et al.
patent: 2007/0109833 (2007-05-01), Pyeon et al.
patent: 2007/0233903 (2007-10-01), Pyeon
patent: 2007/0233917 (2007-10-01), Pyeon et al.
patent: 2007/0234071 (2007-10-01), Pyeon
patent: 2008/0016269 (2008-01-01), Chow et al.
patent: 2008/0140899 (2008-06-01), Oh et al.
patent: 2008/0140916 (2008-06-01), Oh et al.
patent: 2008/0168296 (2008-07-01), Oh et al.
patent: 2008/0226004 (2008-09-01), Oh
patent: 2008/0246504 (2008-10-01), Surico et al.
patent: 2009/0097342 (2009-04-01), Tseng et al.
patent: 1281775 (1991-03-01), None
patent: WO 2005/069150 (2005-07-01), None
patent: WO 2006/036811 (2006-04-01), None
patent: PCT/CA2007/002092 (2008-02-01), None
patent: PCT/CA2008/000237 (2008-05-01), None
patent: PCT/CA2007/002068 (2008-09-01), None
PCT/CA2007/002068 (ISR), Sep. 2, 2008, Mosaid Technologies.
“HyperTransport TM I/O Link Specification”, Revision 2.00b, Document # HTC20031217-0036-0010, HyperTransport Technology Consortium, Apr. 27, 2005, pp. 1 to 325.
PCT/CA2007/002092 (ISR), Feb. 26, 2008, Mosaid Technologies.
PCT/CA2008/000237 (ISR), May 20, 2008, Mosaid Technologies.
Stephen L. Diamond, “SyncLink: High-speed DRAM for the future”, Micro Standards, IEEE Micro, Dec. 1996, pp. 74-75.
Stein Gjessing et al., “A RAM link for high speed”, IEEE Spectrum, Oct. 1992, pp. 52-53.
Stein Gjessing et al., “RamLink: A High-Bandwidth Point-to-Point Memory Architecture”, Copyright 1992 IEEE, pp. 328-331.
Stein Gjessing et al., “Performance of the RamLink Memory Architcture”, Copyright 1994 IEEE, pp. 154-162.
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Yoichi Oshima et al., “High-Speed Memory Architectures For Multimedia Applications”, IEEE, Circuits & Devices, Jan. 1997, pp. 8-13.
Joseph Kennedy et al.,“A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsystems”,IEEE ISSCC 2004/Session 11/DRAM/11.8,10 pgs.
Jae-Kwan Kim et al., “A 3.6Gb/s/pin Simultaneous Bidirectional (SBD) I/O Interface for High-Speed DRAM”, IEEE ISSCC 2004 / Session 22 / DSL and Multi-Gb/s I/O / 22.7, 8 pgs.
Craig L. King et al., “Communicating with Daisy Chained MCP42XXX Digital Potentiometers”, Microchip AN747, 2001 Microchip Technology Inc., 8 pages.
“1024K I2CTM CMOS Serial EEPROM”, Microchip 24AA1025/24LC1025/24FC1025, 2006 Microchip Technology Inc., 22 pages.
“How to Use OTP Registers for Security Applications”, Application Note 717, Oct. 1999, Intel Corporation, 10 pages.
Intel, “Clocking—Lecture 2 and 3, Purpose—Clocking Design Topics”, http://download.intel.com/education/highered/signal/ELCT865/Class2—3—4—Clocking.ppt, Dec. 4, 2002, 42 pages.
Atmel—“8-megabit 2.5-volt Only or 2.7-volt Only DataFlash”—AT5DB081B, Rev. 2225H-DFLSH-10/04, Atmel Corporation 2004, 33 pages.
ST—M25P20—“2Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface”, Aug. 2005, STMicroelectronics, 40 pages.
SST—“16 Mbit SPI Serial Flash”—SST25VF016B, Preliminary Specifications, 2005 Silicon Storage Technology, Inc., 28 pages.
“The I2C-Bus Specification”, Version 2.1, Jan. 2000, Philips Semiconductors, 46 pages.
FBDIMM—“DDR2 Fully Buffered DIMM” 240pin FBDIMMs based on 512Mb C-die (RoHS complaint)—DDR2 SDRAM, Rev. 1.3—Sep. 2006, Samsung Electronics, 32 pages.
K9K8G08U1M—K9F4G08U0M—“K9XXG08UXM”—Preliminary Flash Memory, Samsung Electronics, 43 pages.
S70GL0IGN00 MirrorBit Flash, Publication No. S70GL0IGN00—00, Revision A, Amendment I, Issue Date Jun. 1, 2005, Spansion LLC, 83 pages.
“IEEE Standard for High-Bandwidth Memory Int

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