Methods and systems for detecting memory address transfer...

Details Methods and systems for detecting memory address transfer... Methods and systems for detecting memory address transfer...

2007-11-06

2007-11-06

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10766743

ABSTRACT:
A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequently, the data ECC check bits are written to a memory and the data ECC check bits enable detection of transfer errors in the address bus. A system for detecting transfer errors in an address bus is also described.

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Anonymous, “Memory Data Error Protection and Sparing using the Power PCI Bridge,” Bae Systems, AN-5, Version 1.0 (Mar. 2000). <http://www.iewsna.baesystems.com/space/pdf/ecc—and—sparing.pdf>.

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