Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-03-24
2003-03-04
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S112000, C711S147000, C711S158000, C711S167000, C710S040000, C710S045000, C710S052000
Reexamination Certificate
active
06530000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to mass data storage device controllers. More particularly, the invention relates to methods and systems for arbitrating access to a disk controller memory.
2. Description of the Related Art
Mass data storage is a critical component of computer systems. Typically, mass storage units consist of nonvolatile memory such as a hard disk, an optical drive or other type of storage device. Computer systems typically also contain volatile system memory, such as random access memory (RAM) circuits. Most personal computers today contain less than 256 megabytes of RAM while the same computers often contain hard disks with up to 10 gigabytes or more of capacity.
The mass storage unit of a computer is used to store programs and data on a nonvolatile basis. Thus, the mass storage device retains data even when the computer and the mass storage device are powered down. Volatile system memory, by contrast, serves as a temporary repository of program code and data. Typically, volatile system memory can be accessed much more quickly than a mass storage device. When a microprocessor requires access to programs or data that are not in system memory, the microprocessor first copies the data from the larger, but slower mass storage device to the system memory. The processor may then quickly access the data from the system memory. Further, under certain conditions, if new or modified data is stored in system memory, the microprocessor writes the data to the mass storage device.
A mass storage unit typically consists of a hard disk and a hard disk controller (HDC). The controller operates the hard disk, formats data as it is written to the disk, checks data as it is read from the disk, communicates the data to and from a host system, and buffers the data so as to compensate for latency and difference in data transfer rates between the hard disk and the host computer system.
Typically, the HDC includes a buffer memory which may be used to buffer data between the disk and the host. Because several functional units, such as the disk, the host, and the local controller, need to interact with the buffer memory, access to the buffer memory must be coordinated in some manner. Thus, the HDC may utilize an access arbiter to negotiate access to the buffer memory among various devices requesting access. However, conventional systems typically utilize arbiters that inefficiently provide fixed amounts of access times to accessing units each access cycle. Thus, conventional systems fail to dynamically accommodate changing utilizations of the buffer memory by the accessing units.
SUMMARY OF THE INVENTION
The present invention is directed to a method and system for arbitrating access to a shared resource of a mass storage device controller. In one embodiment of the invention, the controller is a hard disk controller and the shared resource is a local buffer memory of the hard disk controller. Several units or circuits within the controller each access the buffer memory to store or retrieve information. These units may include a controller microprocessor, a host interface unit, a disk formatter unit, a buffer memory refresh unit, a disk format data fetch unit, and an error correction unit. In arbitrating access to the buffer memory, the various access requirements of the units are taken into account. For example, in one embodiment, the disk controller has the most time critical, predictable and periodic access requirements, the other units have less critical and less predictable access requirements, and the host interface unit has the least predictable and least time critical access requirements.
A system according to one embodiment of the present invention operates in a cycle during which each unit is offered continuous access duration. The disk formatter, having the most critical access requirements, is offered periodic access such that the time delay during which it does not have access does not exceed a specified period.
At the high level, the access cycle is bifurcated into two parts. A first part represents the time during which the disk formatter accesses the buffer memory. The second part of the access cycle represents the time during which the remaining units, that is, the units other than the disk formatter, access the buffer memory. However, while the remaining units access the buffer memory, the disk formatter cannot access the buffer memory. In one embodiment, to ensure that the disk formatter is guaranteed periodic access within a predetermined amount of time, the combined access time of the remaining units is limited to a predetermined amount. Similarly, in order to ensure that the remaining units receive access, the access time of the disk formatter is also limited to a predetermined amount. As each of the two parts of the access cycle has a maximum duration, the access cycle itself has a maximum allowed duration.
At the next level, the part of the access cycle allocated to the remaining units is again divided up. Each of the remaining units is allocated a maximum amount of time within the time allocated to the remaining, non-disk formatter units. If any of the remaining units do not use their maximum allocation, the unused time is offered to the last of the remaining units. If the last unit does not use all of the time available to it, the arbitration cycle terminates early. Thus, the time before which the disk formatter is again offered access to the buffer memory ends up being shorter than the specified maximum duration.
In one embodiment, during an access cycle, time is deducted from the total access time allocated to the remaining units as each of the remaining units sequentially utilizes a portion of the total allocated time. Whatever remains of the allocated time after all but the last unit has been offered access, is allocated to the last unit.
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Campbell Frank W.
Krantz Leon A.
Gossage Glenn
Qlogic Corporation
TJ Singh & Klein, O'Neill & Singh
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